Reverse-Bias Step-Stress of Normally-Off GaN Power FETs at Different Temperatures P. Cova, N. Delmonte, F. Giuliani, R. Menozzi University of Parma, Italy Department of Information Engineering Milan - Italy, May 29th, 2014

Normally-Off GaN FET Power Switch EPC 2015 GaN-on-Si VDSMAX = 40 V IDCMAX = 33 A RON = 4 mW VTH = 1.4 V

Reverse-Bias Step-Stress Two-Terminal (S floating) VDGSTART = 40 V VDGSTEP = 5 V tSTEP = 20 min T = 250, 300, 350, 400 K In-situ at-temperature characterization between stress steps (to limit recovery)

300 K Step-Stress BD walkout for short stress times Recovery between stress steps

300 K Step-Stress BD walkout for short stress times (electron trappping between D & G) Recovery between stress steps 40 V 45 V 50 V 55 V 60 V 65 V 70 V

300 K Step-Stress BD voltage decrease for long stress times 70 V 75 V

300 K Step-Stress Same behavior at other temperatures

300 K Step-Stress 3 phases observed during stress: (1) gate leakage reduction (BD walkout) (2) noisy gate current (3) rapid gate leakage degradation leading to failure Similar behavior in Meneghini et al., APL, 100, 033505, 2012. Phase 3 attributed to defect percolation

300 K Step-Stress BD walkout below VDG = 32 V even in phase 3

T-Dependent Step-Stress No clear T dependence of failure voltage

T-Dependent Step-Stress Some dependence on leakage at t = 0? Would be consistent with defect percolation

T-Dependent Step-Stress VTH decrease also in Meneghini et al., APL, 100, 033505, 2012 (hole trapping).

Device degradation mechanism “Low”-voltage stress (VDG < 55 V) GATE BD walkout DRAIN VTH decrease - - - - - + + + + leakage current + - high-field area impact ionization GaN Si

Device degradation mechanism High-voltage stress (VDG > 70 V) GATE BD walkout DRAIN - - - - - - - - - - - - - - - + + + + + - high-field area impact ionization leakage current GaN Si

Device degradation mechanism Low-bias (VDG < 32 V) characterization after high-voltage stres GATE BD walkout DRAIN - - - - - - - - - - - - - - - + + + + leakage current high-field area GaN Si

Device degradation mechanism STRESS BD walkout below VDG = 32 V even in phase 3

To-do list More FETs stress at various temperatures Investigate link between VFAIL and leakage at t = 0 Test different combinations of stress step Dt and DV Physical simulations, once known the device structure, to support results interpretation and study for improvements