FEB v2 Status Y. Favre 15 March 2017.

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Presentation transcript:

FEB v2 Status Y. Favre 15 March 2017

Reception of x6 FEBv2: 13 March 2017 Photo: 14 March 2017

FEBv2 in MiniCrate: 15 March 2017

Status 1/3 Status COMPLETED : Identical to FEB V1 functionalities all power supplies are OK FPGA programming OK USB µC programming OK USB readout software recognizes the board & FPGA firmware version HV ON/OFF OK ASIC & FPGA parameters configuring OK Readout tests with 3 SiPM channels per ASIC OK

Status 2/3 Status TO BE DONE (new FEB V2 features): Readout tests with all 96 channels (ETAM) SYNC IN/OUT (CLK + SYNC) Independent channel HV ON/OFF with RS485 HVON short-circuit/current limit test 5V µC HVON short-circuit/current limit test Addressing (Slots/MCR address) through backplane Programming through backplane GSTART/GRESET/GSPILL input test RX/TX 1Mb/s Protocol Chain Next/Prev Gigabit Readout Chain Housekeeping sensors

Status 3/3 Status TO BE DONE (new FEB V2 features, no priority): AUX IN, TX OUT (not used in B-MIND) RTS/CTS 1Mb/s Protocol Chain (future use in B-MIND) 2nd Next/Prev Gigabit Readout Chain (future use to increase bandwidth in MCR chain in B-MIND)

First fingerplot: 14th March 2017 Baseline lowered compared to FEBv1 to increase dynamic range!!

Three channels per ASIC: ASIC 0

Three channels per ASIC: ASIC 1

Three channels per ASIC: ASIC 2