Mikhail Chupilko, Alexander Protsenko

Slides:



Advertisements
Similar presentations
Digital System Design-II (CSEB312)
Advertisements

CMSC 611: Advanced Computer Architecture
OBJECTIVES Learn the history of HDL Development. Learn how the HDL module is structured. Learn the use of operators in HDL module. Learn the different.
Sequential Logic in Verilog
Introducing Formal Methods, Module 1, Version 1.1, Oct., Formal Specification and Analytical Verification L 5.
Runtime Verification Based on Executable Models: On-the-Fly Matching of Timed Traces Mikhail Chupilko, Alexander Kamkin.
CSE 201 Computer Logic Design * * * * * * * Verilog Modeling
Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi
The Design Process Outline Goal Reading Design Domain Design Flow
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.
1 Advanced Material The following slides contain advanced material and are optional.
Dr. Pedro Mejia Alvarez Software Testing Slide 1 Software Testing: Building Test Cases.
Using Mathematica for modeling, simulation and property checking of hardware systems Ghiath AL SAMMANE VDS group : Verification & Modeling of Digital systems.
Contract Specification of Pipelined Designs Alexander Kamkin Institute for System Programming of RAS
Model-based Methods for Web Service Verification.
Benjamin Gamble. What is Time?  Can mean many different things to a computer Dynamic Equation Variable System State 2.
An Introduction to Digital Systems Simulation Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA)
L16 – Testbenches for state machines. VHDL Language Elements  More examples HDL coding of class examples Testbench for example  Testing of examples.
Using Formal Verification to Exhaustively Verify SoC Assemblies by Mark Handover Kenny Ranerup Applications Engineer ASIC Consultant Mentor Graphics Corp.
Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.
VHDL IE- CSE. What do you understand by VHDL??  VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.
Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in.
A Light-Weight C/C++ Based Tool for Hardware Verification Alexander Kamkin CTestBench Institute for System Programming of the Russian.
Functional Verification Figure 1.1 p 6 Detection of errors in the design Before fab for design errors, after fab for physical errors.
Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.
Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 11 High Desecration Language- Based Design.
IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.
Using Cycle-Accurate Contract Specifications for Testing Hardware Models Alexander Kamkin Institute for System Programming of RAS
Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 1 Digital Fundamentals.
Time Abstraction in Simulation-Based Hardware Verification Alexander Kamkin Institute for System Programming of the Russian Academy of.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
Parallelizing Functional Tests for Computer Systems Using Distributed Graph Exploration Alexey Demakov, Alexander Kamkin, and Alexander Sortov
VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.
Lecture 1 – Overview (rSp06) ©2008 Joanne DeGroat, ECE, OSU -1- Functional Verification of Hardware Designs EE764 – Functional Verification of Hardware.
EECE 320 L8: Combinational Logic design Principles 1Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 8: Combinational Logic Design Principles.
1 A hardware description language is a computer language that is used to describe hardware. Two HDLs are widely used Verilog HDL VHDL (Very High Speed.
Logic Simulation 1 Outline –Logic Simulation –Logic Design Description –Logic Models Goal –Understand logic simulation problem –Understand logic models.
Hardware Description Languages: Verilog
Adapted from Krste Asanovic
Andreas Hoffmann Andreas Ropers Tim Kogel Stefan Pees Prof
Basic Language Concepts
HDL simulation and Synthesis (Marks16)
Verilog-HDL-1 by Dr. Amin Danial Asham.
Topics Modeling with hardware description languages (HDLs).
Digital System Verification
Hardware Description Languages: Verilog
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Topics Modeling with hardware description languages (HDLs).
Assertions An assertion is a statement about the design’s intended behavior Assertions can be written in a hardware description language (HDL) Assertions.
Topics HDL coding for synthesis. Verilog. VHDL..
ECE 434 Advanced Digital System L08
Hardware Description Language
STATIC TIMING ANALYSIS, CROSS TALK AND NOISE
Hardware Description Languages
RTL Design Methodology
Verilog for Digital Design
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
Detecting and Resolving Model Errors
Event-Based Architecture Definition Language
Model-based testing of complex manufacturing systems: A case study
Digital Design Verification
RTL Design Methodology
Design Methodology & HDL
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Presentation transcript:

Mikhail Chupilko, Alexander Protsenko Recognition and Explanation of Incorrect Behavior in Simulation-Based Hardware Verification Mikhail Chupilko, Alexander Protsenko

Outline Development of hardware models Test system architecture Establishing of conformance Trace event recombination Examples Conclusion

Hardware model design They are developed in Hardware Description Languages, like Verilog or VHDL The result of development is the program being executed in HDL simulator The common approach for verification of hardware models is testing of HDL programs To automatize testing is possible by means of executable models (e.g. in C++)

HDL programs input S; CLK output R1, R2; void design() { S while(true) { wait(S); delay(6); R1 = 1; delay(1); R1 = 0; R2 = 1; R2 = 0; } CLK S R1 R2 6 cycles Parallel assignments

Hardware model behavior

Reference model-based test oracle HDL Test oracle Reference model Reference model reactions Reaction arbiters Input interface adapters Output interface adapters Stimuli Reaction comparators HDL-model reactions

Typical representation of verification results Data on so-and-so wire are not correct, the correct data are… More advanced: data in so-and-so packet generated on so-and-so step are not valid… The most advanced: data in so-and-so packet should be received on the following cycle, but they were confused with the following packet…

Example of the bug found 0xf953e8d83a9b9209  0x19c3827ab2920e58 0x19c3827ab2920e58  0xf953e8d83a9b9209 8

Reference model-based test oracle HDL Test oracle Reference model Reference model reactions Reaction arbiters Input interface adapters Output interface adapters Stimuli Reaction comparators HDL-model reactions Diagnostics subsystem

Conformance reaction checking If there is a rearrangement of reference model reactions, where properties of data, iface equality and time restrictions are satisfied

If there is a problem…  

Simplified diagnostics process based on trace of reactions  

Recombination of reactions with requirement of total equal in data (null, null) -> remove the pair; (x, x) -> (null, null); {(x, y), (y, x)} -> {(x, x), (y, y)}; {(x, null), (null, x)} -> (x, x); {(x, y), (y, null)} -> {(x, null), (y, y)}; {(x, y), (null, x)} -> {(x, x), (null, y)}; {(x, z), (y, x)} -> {(x, x), (y, z)};

Recombination of reactions with requirement of partial equal in data {(x, y), (y`, x`)} -> {(x, x`), (y`, y)}; {(x, null), (null, x`)} -> (x, x`); {(x, y`), (y, null)} -> {(x, null), (y, y`)}; {(x, y), (null, x`)} -> {(x, x`), (null, y)}; (x, x`) -> (null, null).

Example-1

Example-2 Part of trace in text form Table with recombination [INCORRECT](iface=output_mau cycle=107): Incorrect reaction: Msg{spec=MAU_pha(0xb0418b0f), impl=MAU_pha(0x96e7741c)}, Msg{spec=MAU_dst_pha(0x6), impl=MAU_dst_pha(0)} expected at [107,157] [INCORRECT](iface=output_mau cycle=105): Incorrect reaction: Msg{spec=MAU_pha(0x96e7741c), impl=MAU_pha(0xb0418b10)}, Msg{spec=MAU_dst_pha(0), impl=MAU_dst_pha(0x6)} expected at [105,155] [INCORRECT](iface=output_mau cycle=98): Incorrect reaction: Msg{spec=MAU_pha(0x5bf9a01e4), impl=MAU_pha(0xb0418b0f)}, Msg{spec=MAU_dst_pha(0x3), impl=MAU_dst_pha(0x6)} expected at [98,148] Table with recombination Explanation based on history of applied rules of recombination

C++TESK Testing ToolKit Web: http://forge.ispras.ru/projects/cpptesk-toolkit E-mail: cpptesk-support@ispras.ru

Conclusion Better representation of verification results means less efforts for their interpretation Application of the rule set allow to regroup reaction pairs finding possible hint of what is going bad in the system behavior The method has been implemented in C++TESK Testing ToolKit and has been successfully used in a number of projects Future research is connected with showing of history usage in diagnostics and/or giving hints to localization of bugs

THANK YOU Any questions?

Example-3

Example-4