von Neumann Architecture CPU

CPU: Central Processing Unit https://www.anandtech.com/show/6985/choosing-a-gaming-cpu-at-1440p-adding-in-haswell-

RAM: Random Access Memory http://www.techgriff.com/nedir/ram-nedir-ne-ise-yarar-2-14853

CPU in von Neumann Architecture CPU Registers Control Unit Arithmetic Logic Unit Circuits for Adder Shifter Multiplier Divider Control Processing Unit (CPU)

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 0000010100110000 Control Unit ALU 0110100111100001 Program Counter 1011100110001100 00000011 0100000000000111 Instruction Register 0000000000011110 00110100 0000100000010000 Control Processing Unit (CPU) 0000000000000001

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 0000010100110000 Control Unit ALU 0110100111100001 Program Counter 1011100110001100 00000011 0100000000000111 Instruction Register 0000000000011110 00110100 0000100000010000 Control Processing Unit (CPU) 0000000000000001 A few fast registers + math circuits Lots of slow registers

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 000001010011000 Control Unit ALU 000100111100001 Program Counter 000000110001100 00000000 100000000000111 Instruction Register 000000000000110 00000000 000000000010000 Control Processing Unit (CPU) 0000000000000001 Programs AND data Fetch-Execute Cycle Runs Program

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 000001010011000 Control Unit ALU 0000100111100001 Program Counter 000000110001100 00000001 100000000000111 Instruction Register 00000000000110 1010011000 000000000010000 Control Processing Unit (CPU) 0000000000000001 Programs AND data Fetch-Execute Cycle Runs Program

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 000001010011000 Control Unit ALU 0000100111100001 Program Counter 000000110001100 00000010 100000000000111 Instruction Register 00000000000110 100111100001 000000000010000 Control Processing Unit (CPU) 0000000000000001 Programs AND data Fetch-Execute Cycle Runs Program

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers 000001010011000 Control Unit ALU 0000100111100001 Program Counter 000000110001100 00000011 100000000000111 Instruction Register 00000000000110 110001100 000000000010000 Control Processing Unit (CPU) 0000000000000001 Programs AND data Fetch-Execute Cycle Runs Program

Von Neumann Architecture CPU Random Access Memory (RAM) CPU Registers Next time Control Unit ALU we'll start Program Counter to run actual 00000011 programs Instruction Register using Hmmm 110001100 Control Processing Unit (CPU) Programs AND data Fetch-Execute Cycle Runs Program

How do programs execute? Problem – a CPU does not execute instructions directly from memory. Instructions need to be brought into the CPU from memory one at a time. The fetch – execute cycle while not halt instruction Fetch instruction from memory and place in Instruction Register(IR) Add one to Program Counter(PC) Decode instruction Execute instruction

More Bits of the implementation… An 8-bit register: s D Q s D Q s D Q s D Q s D Q s D Q s D Q s D Q Registers are an integral part of every CPU (Nothing more than collection of D Flip Flops!) The PC register holds the memory address of the next instruction. Program Counter PC The IR register holds the instruction to be executed. Instruction Register IR A register is only a collection of D Flip flops. Data registers can be used as the programmer wishes. But who is this hypothetical programmer? Reg3 Reg4 A Control Unit (CU) keeps all of the logic in sync and keeps track of what needs to be done next… 1 1 0 0 0 0 0 CU 2 0 1 0 0 0 0 3 0 0 1 0 0 0 4 0 0 0 1 0 0 5 0 0 0 0 1 0

RAM CU ripple8 a Von Neumann machine 05 addn r3, 4 1 7+4 4 strobe PC IR Reg3 1 The instruction Argument 1 Argument 2 the same Reg3 the register the constant 4 old value of Reg3 = 7 new value of Reg3 = 11 CU read enable RAM 8 data bits 8 address bits strobe for all IR bits D in Q out decode instruction strobe to finish instruction (to all bits) ripple8 7+4 8 output bits flip-flop strobe for next instruction Instruction Decoding Guide 2 3 5 05 addn r3, 4 Just explain the pieces. This is a SIMPLE model! Direct their attention to the bottom right table. It's a simple 4 instruction machine! More to come.... 00 = LOAD from memory 01 = STORE to memory 10 = add a constant to a reg. (addn) a Von Neumann machine 11 = ADD a reg. to a reg.