VLSI Design MOSFET Scaling and CMOS Latch Up UNIT III : VLSI CIRCUIT DESIGN PROCESSES 01/02/2009 VLSI Design VLSI Design

Out Line MOSFET Scaling CMOS Latch Up VLSI Design

Why Scaling? Die cost decreases Operation speed increases But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction VLSI Design

Technology has scaled well, will it in the future? Technology Scaling GATE GATE SOURCE BODY DRAIN Xj DRAIN SOURCE D Tox BODY Leff Dimensions scale down by 30% Doubles transistor density Oxide thickness scales down Faster transistor, higher performance Vdd & Vt scaling Lower active power Technology has scaled well, will it in the future? VLSI Design

MOSFET scaling High density chip The sizes of the transistors are as small as possible The operational characteristics of MOS transistor will change with the reduction of iys dimensions There are two basic types of size-reduction strategies Full scaling (constant-field scaling) Constant-voltage scaling A new generation of manufacturing technology replaces the previous one about every two or three years The down-scaling factor S about 1.2 to1.5 The scaling of all dimensions by a factor of S>1 leads to the reduction of the area occupied by the transistor by a factor of S2 VLSI Design

VLSI Design

Technology Evolution Currently, the feature size is 45 nm Technology. VLSI Design

Technology Scaling Models VLSI Design

1.constant-field scaling (Full scaling ) Two types of scaling methodologies 1.Constant Filed scaling (Full scaling) 2.Constant Voltage scaling 1.constant-field scaling (Full scaling ) VLSI Design

Constant Field Scaling VLSI Design

Full scaling (constant-field scaling) VLSI Design

Constant-voltage scaling VLSI Design

Constant Voltage scaling VLSI Design

Constant-voltage scaling VLSI Design

Scaling challenges L, VDD, VT scaling  Increasing parameter variation  Increasing sub-threshold leakage power  Increasing tunneling current Product life cycle reduced from 3.6 years to 2 years  Concurrent engineering  Better prediction models Things become smaller. Variation becomes larger. Worse S/N ratio. VLSI Design

. CMOS Latch UP VLSI Design

CMOS Latchup There is one major downfall to the CMOS logic gate – Latchup There are many safeguards that are done during fabrication to suppress this, but it can still occur under certain transient or fault conditions VLSI Design

CMOS Inverter Technology The CMOS inverter consists of a PMOS stacked on top on a NMOS, but they need to be fabricated on the same wafer To accomplish this, the technique of “n-well” implantation is needed as shown in the figure which shows the cross-section of a CMOS inverter VLSI Design

Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures. VLSI Design

CMOS Latchup Latchup occurs due parasitic bipolar transistors that exist in the basic inverter as shown below VLSI Design

Latchup in CMOS Devices VLSI Design 21

Parasitic SCR circuit I-V behavior VLSI Design

Parasitic Transistors Parasitic bipolar transistors form at N/P junctions Latchup - when parasitic transistors turn on Preventing latchup: Add substrate contacts (“tub ties”) to reduce Rs, Rw (more about this later) OR Use Silicon-on-Insulator VLSI Design

Latch-Up Occurs when parasitic bipolar transistors are turned on Shorts Vdd to GND Persists indefinitely Requires power cycle or causes component failure Avoidable if Rw and Rs are small V n + p out in dd GND R w s p-well N-substrate PNP NPN VLSI Design

Controlling Latchup - Substrate Contacts Purpose: connect well/substrate to power supply Alternative term: tub tie (used by book) Recommendations (source: Weste & Eshraghian) Conservative: 1 substrate contact for every supply connection Less conservative: 1 substrate contact for every 5-10 transistors High-current circuits: use guard rings Substrate Contact Substrate Contact VLSI Design

Improving Latch-Up Immunity Improve isolation Epitaxial layer grow single crystal silicon on wafer greatly reduces Rs Trench isolation deep trenches of SiO2 as insulators isolates well from substrate Add lots of substrate and well contacts Maximum distance between contact and FET No more than 20-30 l One contact per 5-10 transistors Minimize distance from source to contact Direct metal contacts (no diffusion) VLSI Design

Solution to latch-up --Use tub ties to connect tub to power rail. --Use enough to create low-voltage connection. VLSI Design

Tub tie layout p+ metal (VDD) p-tub VLSI Design

References CMOS Digital Integrated Circuits Analysis And Design, Sung-mo Kang,Yusuf Leblebici CMOS VLSI design, Neil H.E.Weste,David Harris,Ayan Banerjee VLSI Design