I2C Synchronous Serial Two wire communications (plus ground)

Slides:



Advertisements
Similar presentations
I2C bus Inter Integrated Circuits bus by Philips Semiconductors
Advertisements

Synchronous Links/Networks Modems are asynchronous - penalized by start bits and stop bits on each character (and dead time) Synchronous Networks recover.
CSE 466 – Fall Introduction - 1 COMMANDS RESPONSES Master/Slave Software Architecture Master void master() _task_ MAST{ Button(mode); // enq(cmd)
Lecture 8: Serial Interfaces
COMT Performance of Data Communications Protocols General Protocol Concepts.
Advanced Operating Systems The I 2 C Bus. Inter-Integrated Circuit Bus Designed for low-cost, medium data rate applications. Characteristics: –Synchronous;
EEC-484/584 Computer Networks Lecture 13 Wenbing Zhao
Host Data Layer 7 Application Interacts with software requiring network communications; identifies partners, resources and synchronization Layer 6 Presentation.
I2CI2C CS-423 Dick Steflik. Inter-Integrated Circuit Developed and patented by Philips for connecting low speed peripherals to a motherboard, embedded.
WXES2106 Network Technology Semester /2005 Chapter 8 Intermediate TCP CCNA2: Module 10.
Two Wire Interface Another popular serial peripheral interface bus -More flexible than SPI -Master and slave modes supported -7-bit slave address -400khz.
Lecture 27: LM3S9B96 Microcontroller – Inter- Integrated Circuit (I 2 C) Interface.
Haptic Belt team Informational Presentation.  I 2 C is a form of control bus (multi-master) which allows communication between multiple integrated circuits.
EECS 373 Controller Area Networks Samuel Haberl Russell Kuczwara Senyuan Zhong.
1 EECS 373 Design of Microprocessor-Based Systems Prabal Dutta University of Michigan Lecture 10: Serial buses Oct 6, 2011.
SERIAL BUS COMMUNICATION PROTOCOLS
1 © Unitec New Zealand I2C Lecture 10 Date: - 2 Nov, 2011 Embedded Hardware ETEC 6416.
LSU 10/22/2004Serial I/O1 Programming Unit, Lecture 5.
VERIFICATION OF I2C INTERFACE USING SPECMAN ELITE By H. Mugil Vannan Experts Mr. Rahul Hakhoo, Section Manager, CMG-MCD Mr. Umesh Srivastva, Project Leader.
Lecture 9. - Synchronous Devices require a timing signal. Clock generated Interval Timer Microprocessor Interval Timer Clk PCLK = MHz PCLK (for.
ECE 493T9 Real Time Embedded System Tutorial Set 3 June 10, Spring 2008.
7/23 Inter-chip Serial Communication: SPI and I 2 C Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang Lee.
Lecture 20: Communications Lecturers: Professor John Devlin Mr Robert Ross.
1 7-Oct-15 OSI transport layer CCNA Exploration Semester 1 Chapter 4.
DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK
Cyclic Redundancy Check (CRC).  An error detection mechanism in which a special number is appended to a block of data in order to detect any changes.
1 Synchronous Serial IO Send a separate clock line with data –SPI (serial peripheral interface) protocol –I 2 C (or I2C) protocol Encode a clock with data.
Refer to Chapter 15 in the reference book
©2008 R. Gupta, UCSD COSMOS Summer 2008 Peripheral Interfaces Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Essentials of Communication This simple model requires many guarantees. Sender Receiver Communication Link Data.
Lab 9 Multiprocessor, Buses, SPI, I2C. Multiprocessors Why multiprocessors? The structure of multiprocessors. Elements of multiprocessors: – Processing.
 The LPC2xxx devices currently have two on- chip UARTS.  Except UART1 has additional modem support.
McGraw-Hill©The McGraw-Hill Companies, Inc., 2000 Lecture 3 : Network Architectures 1.
UNIT 24 I2C Test 로봇 SW 교육원 조용수.
Serial Communication Originally created by Anurag Dwidedi and Rudra Pratap Suman.
Outline Analog to digital conversion (ADC) of NuMaker TRIO
The I2C Bus.
Two Wire Interface Another popular serial peripheral interface bus
Lab 7 – CSMA/CD (Data Link Layer Layer)
EE 107 Fall 2017 Lecture 5 Serial Buses – UART & SPI
Inter-IC Bus (I C) 2.
Chapter 11: Inter-Integrated Circuit (I2C) Interface
(Inter-IC bus) By Tejaswini Gadicherla
EE 107 Fall 2017 Lecture 7 Serial Buses – I2C Direct Memory Access
Basic PIC-C I2C Communication
I2C Protocol and RTC Interfacing
I2C PROTOCOL SPECIFICATION
Communication Lines Fundamentals.
IOS Network Model 2nd semester
CS 457 – Lecture 6 Ethernet Spring 2012.
Introduction of Transport Protocols
Zephyr Device Driver and Device Model
BJ Furman ME 106 Fundamentals of Mechatronics 15NOV2012
EEPROM Comparison – Parallel or Serial
Computer Organization and Design
NetSilicon & Digi Confidential
Asynchronous Serial Communications
I2C and RTC Chapter 18 Sepehr Naimi
Getting Connected (Chapter 2 Part 3)
I2C Protocol and RTC Interfacing
Principles of Computers 20th Lecture
Data Communication Networks
Lecture 5- Data Link Layer
Controller Area Networks (CAN)
I2C Protocol and RTC Interfacing
Another Physical Layer – I2C
DATA COMMUNICATION Lecture-38.
Networking CS 3470, Section 1 Sarah Diesburg
Serial Communication 19th Han Seung Uk.
Dr. John P. Abraham Professor UTPA
Presentation transcript:

I2C Synchronous Serial Two wire communications (plus ground) SCL – clock line SDA – bi-directional data line Message length: unrestricted Master – Slave Network Master Controls the information flow Source of SCL Slave Can synchronize data transfer by introducing wait states 9/12/2018 ECE 340 Lecture 24

I2C Synchronous Serial Multi-drop communications: Multiple transmitters and receivers on a common communications conductor Broadcast communications is possible One sender – many listeners Collision arbitration is required for multiple masters 9/12/2018 ECE 340 Lecture 24

I2C Definitions TERM DESCRIPTION Transmitter: The device which sends data to the bus Receiver: The device which receives data from the bus Master: The device which initiates a transfer, generates clock signals and terminates a transfer Slave: The device addressed by a master Multi-master: More than one master can attempt to control the bus at the same time without corrupting the message Arbitration: Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Synchronization: Procedure to synchronize the clock signals of two or more devices 9/12/2018 ECE 340 Lecture 24

I2C Physical Layer 9/12/2018 ECE 340 Lecture 24

I2C Framing 9/12/2018 ECE 340 Lecture 24

I2C Bit Transfer 9/12/2018 ECE 340 Lecture 24

I2C Byte Transfer Bit States Recessive (high == 1) Dominate (low == 0) 9/12/2018 ECE 340 Lecture 24

I2C Acknowledge 9/12/2018 ECE 340 Lecture 24

I2C Address 9/12/2018 ECE 340 Lecture 24

I2C Packet 9/12/2018 ECE 340 Lecture 24

Master Write Packet NACK – “Not ACKnowldege” can be used by slave to terminate packet 9/12/2018 ECE 340 Lecture 24

Master Read Packet Specification calls for Master to terminate with a NACK and a Stop bit 9/12/2018 ECE 340 Lecture 24

Master Write / Read Packet If changing direction of data transfer, then the master must resend the address in order to change the value of the R/W bit 9/12/2018 ECE 340 Lecture 24

“Mystery Code” int ReadIOXPort(unsigned char port) { #define IOX0 0x76 #define I2C_READ 0x01 // R/W bit char data_byte; int err; if(!port) // Assign I2C Address to Port Number port = IOX0; else port = IOX1; if (err=i2c_start_tx()) { // Start bit i2c_stop_tx(); return 0xff00 | err; } // Stretching error if (err=i2c_write_char(port + I2C_READ)) { // Send Address i2c_stop_tx(); return 0xfe00 | err; } // Stretching error If (err=i2c_read_char(&data_byte)) { // Read data i2c_stop_tx(); return 0xfc00 | err; } // Stretching error i2c_send_ack(); // Acknowledge data i2c_stop_tx(); // Stop bit return (unsigned int) data_byte; } // end ReadIOXPort “Mystery Code” 9/12/2018 ECE 340 Lecture 24

“Bit Banging” // Define these to change basic bit handling #define i2c_SCL_H() BitWrPortI(PDDDR,&PDDDRShadow,0,I2CSCLBit) #define i2c_SCL_L() BitWrPortI(PDDDR,&PDDDRShadow,1,I2CSCLBit) #define i2c_SDA_H() BitWrPortI(PDDDR,&PDDDRShadow,0,I2CSDABit) #define i2c_SDA_L() BitWrPortI(PDDDR,&PDDDRShadow,1,I2CSDABit) #define i2c_SCL() BitRdPortI(PDDR,I2CSCLBit) // read SCL #define i2c_SDA() BitRdPortI(PDDR,I2CSDABit) // read SDA 9/12/2018 ECE 340 Lecture 24

Clock Stretching int i2c_wSCL_H(){ // Tries to set SCL high & waits // Returns -1 if SCL stretch too long auto int delay_cnt; i2c_SCL_H(); cWAIT_5_us; // Set SCL HI delay_cnt = 0; while(i2c_SCL()==0 && delay_cnt < i2cClockStretchDelay) { cWAIT_5_us; delcnt++; } // end while if (i2c_SCL()==0) return -1; // Clock stretch too long return 0; } // end i2c_wSCL_H() 9/12/2018 ECE 340 Lecture 24

Start, Stop, & Ack int i2c_start_tx(){ // Try to send start pulse. // If clock stretch exceeded, return -1 else 0 if (i2c_wSCL_H()) return -1; // Try to set SCL HI i2c_SDA_H(); cWAIT_5_us; // Set SDA HI i2c_SDA_L(); cWAIT_5_us; // Set SDA LO i2c_SCL_L(); return 0; // Set SCL LO } // end i2c_start_tx void i2c_stop_tx() { i2c_SDA_L(); cWAIT_5_us; i2c_SCL_H(); cWAIT_5_us; i2c_SDA_H(); } // end i2c_stop_tx int i2c_send_ack() { i2c_SDA_L(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; cWAIT_5_us; i2c_SCL_L(); cWAIT_5_us; i2c_SDA_H(); return 0; } // end i2c_send_ack 9/12/2018 ECE 340 Lecture 24

Write Char int i2c_write_char(char d){ // Writes char; returns -1 if no ACK from remote auto char i; for (i=0; I < 8; i++) { if (d & 0x80) i2c_SDA_H(); // send bit else i2c_SDA_L(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; // Set SCL HI i2c_SCL_L(); cWAIT_5_us; // Set SCL LO d = d << 1; } // end for return i2c_check_ack(); } // end i2c_write_char() 9/12/2018 ECE 340 Lecture 24

Do you see any opportunities for improvement? Read char int i2c_read_char(char *ch) { auto char res,cnt; for ( cnt=0,res=0; cnt<8; cnt++ ) { i2c_SDA_H(); cWAIT_5_us; if (i2c_wSCL_H()) return -1; res <<= 1; if (i2c_SDA()) res |= 0x01; i2c_SCL_L(); cWAIT_5_us; } // end for *ch=res; return 0; } // end i2c_read_char Do you see any opportunities for improvement? 9/12/2018 ECE 340 Lecture 24

I2C on UI Project PCB 9/12/2018 ECE 340 Lecture 24

PCF8574 I2C Expander Can accommodate up to 8 devices on one I2C network 9/12/2018 ECE 340 Lecture 24

PCF8574 I2C Expander 9/12/2018 ECE 340 Lecture 24

Multi-Master I2C Network 9/12/2018 ECE 340 Lecture 24

I2C Arbitration 9/12/2018 ECE 340 Lecture 24

I2C Arbitration for 2 Masters 9/12/2018 ECE 340 Lecture 24

I2C References Specification: Tutorials http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf Tutorials Introduction to I2C (http://www.embedded.com/story/OEG20010718S0073) 9/12/2018 ECE 340 Lecture 24

Quiz List, and briefly describe, differences between RS232 and I2C communication in the Rabbit environment. Do see anything wrong with this? If (err=i2c_read_char(&data_byte)) { // Read data i2c_stop_tx(); return 0xfc00 | err; } // Stretching error 9/12/2018 ECE 340 Lecture 24