Chapter 2. Introduction To VHDL RTLAB 권일근 2002년 1월 2일

VHDL Description Of Combinational Networks Entity-Architecture Pairs entity entity-name is [port (interface-signal-declaration);] end [entity] [entity-name]; architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture] [architecture-name]; list-of interface-signals: mode type [:= initial–value] {; list-of-interface-signals: mode type [:= initial-value]} mode: in, out, inout (bidirectional)

Ex) entity FullAdder is port (X, Y, Cin: in bit; Cout, Sum: out bit); end FullAdder; architecture Equation of FullAdder is begin Sum <= X xor Y xor Cin after 10ns; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 10 ns; end Equation; *) --: Comment <=: signal assignment.

VHDL Program Structure Entity Architecture Entity Architecture Module 1 Entity Architecture Module 2 Entity Architecture Module 3

process (sensitivity-list) Using VHDL Process process: a common way of modeling sequential logic in VHDL process (sensitivity-list) begin sequential-statements end process; if if condition then sequential statements {elsif condition then sequential statements} -- 0 or more elsif clauses may be included [else sequential statements] end if;

VHDL Models For A Multiplexer MUX I1 F I2 I3 A B

Conditional Assignment Statement F <= I0 when Sel = 0 else I1 when Sel = 1 else I2 when Sel = 2 else I3; case Sel is when 0 => F <= I0; when 1 => F <= I1; when 2 => F <= I2; when 3 => F <= I3; end case;

Modeling A Sequential Machine Behavioral Model Data-flow Model Structural Model wait-statement: uses instead of a sensitivity list. wait on sensitivity-list; wait for time-expression; wait until boolean-expression;

Variables, Signals, And Constants variable list_of variable_names : time_name [:= initial_value] signal list_of_signal_name : type_name [:= initial_value] constant constant_name : type_name := constant_value locality variable process, function, procedures signal architecture constant process, function, procedures, architecture type state_type is (S0, S1, S2, S3, S4, S5); signal state : state_type : = S1;

Arrays type SHORT_WORD is array (15 downto 0) of bit signal DATA_WORD: SHORT_WORD; variable ALT_WORD: SHORT_WORD:= “01010101…”; constant ONE_WORD: SHORT_WORD:= (others => ‘1’); type matrix4x3 is array (1 to 4, 1 to 3) of integer; variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6), (7, 8, 9), (10, 11, 12)); type intvec is array (natural range <>) of integer; signal intvec5: intvec (1 to 5) := (3, 2, 6, 8, 1);

Operator Binary logical operatoors: and or nand nor xor xnor Relational operator: = /= < <= > >= Shift operator: sll srl sla sra rol ror Adding operators: + - &(concatenation) Unary sign operators: + - Multiplying operator: * / mod rem Miscellaneous operators: not abs **

Functions function function_name (formal-parameter-list) return return-type is [declaration] begin sequential statements – must include return return-value; end function-name; The general form of a function call is function_name (actual-parameter-list) [loop-label:] for loop-index in range loop sequential statements end loop [loop-label];

Procedures procedure procedure_name (formal-parameter-list) is [declaration] begin sequential statements end procedure-name; procedure_name (actual-parameter-list);

Packages And Library package package_name is package declarations end [package][package_name]; package body package_name is package body declarations end [package body][package_name]; library, use ex) library BITLIB; use BITLIB.bit_pack.all;