External CPU Bus Activity Example problem: (a) What will be the logic levels on the external SRC buses when each of the following SRC instruction is executing on the processor? Complete the table given. All numbers are in the decimal number system, unless noted otherwise. (b) Specify memory addressing modes for each of the SRC instructions given. SRC Instruction RTL equivalent Address Bus <31..0> Data Bus MRead MWrite ld r7, 12(r5) ld r2, 32 la r9, 32 ldr r12, -4 lar r3, 0 st r2, 0(r6) str r3, -8 st r4, 32

Assumptions: All memory content is aligned properly. In other words, all the memory accesses start at addresses divisible by 4. (cf. p98, H&J) Value in the PC = 000DC348h

Review

CS501 Advanced Computer Architecture Lecture 15 Dr.Noor Muhammad Sheikh

Memory Map with assumed values Address Memory Content 00000020h D2h 00000021h 96h 00000022h 49h 00000023h 2Fh ………… ……… 000DC300h 44h 000DC301h 23h 000DC302h E3h 000DC303h D5h ……………. ….. 000DC340h 51h 000DC341h CAh 000DC343h D5h 000DC344h E2h …………… …… 00AB1240h 07h 00AB1241h 85h 00AB1242h E5h 00AB1243h 3Dh

Register Map with assumed values Register Name Content R[0] 0012A54Bh R[1] 10234CB8h R[2] D296492Fh R[3] 001400CDh R[4] B7432301h R[5] 00AB1234h R[6] 00000020h R[7] 01432D7Fh R[8] 00B94821h R[9] 00CDA7A3h R[10] 0031A0F0h R[11] 0012A246h R[12] 000FAB17h Register Map with assumed values

Solution Part (a): SRC Instruction RTL equivalent Address Bus* <31..0> Data Bus MR MW ld r7, 12(r5) R[7] M[12+R[5]] 00AB1240h 0785E53Dh 1 ld r2, 32 R[2] M[32] 00000020h D296492Fh la r9, 32 R[9] 32 Unknown ? ldr r12, -4 R[12] M[PC-4] 000DC344h 4423E3D5h lar r3, 0 R[3] PC st r2, 0(r6) M[R[6]] R[2] str r3, -8 M[PC-8] R[3] 000DC340h 001400CDh st r4, 32 M[32] R[4] B7432301h * SRC uses big-endian convention

Solution part (b): SRC Instruction Addressing Mode ld r7, 12(r5) la r9, 32 ldr r12, -4 lar r3, 0 st r2, 0(r6) str r3, -8 st r4, 32 Displacement Direct Immediate PC Relative Register Register Indirect PC Relative Register Direct

MAR Connections MAR MRead from CPU’s data bus 3-state buffers LMAR to internal bus 3-state buffers MARout

MBR connections MBR MRead INT2MBR from CPU’s data bus from internal bus 3-state buffers 3-state buffers LMBR MBR to CPU’s data bus to internal bus 3-state buffers 3-state buffers MWrite MBRout

Complete view of 1-Bus SRC design 31 0 <31..0> R0 31 0 R1 PC General purpose registers (32-bits each) 32 lines CON Logic IR 32 Select logic R31 32 A to memory sub system MAR A B MBR ALSU 4 0 n decrement C Internal processor bus

Generating control signals for the register file ….. 31…27 26…22 21…17 16…12 11 IR opc ra rb rc Control signals to register file RAE 5 5 5 RCE RBE LR0 LR1 LR31 BUS2R ….. R0 R1 R31 R0out R0 5 5-to-32 decoder R1out R1 ….. R31out R31 R2BUS

Alternate control circuitry for register select ….. IR opc ra rb rc Repeat 32 times 5 R0A 5 R0C R0 LR0 5 R1C R0B R0B ….. R1B 5-to-32 decoder LR1 R0A R0C ….. R1 ….. R1A 5-to-32 decoder R31C ….. ….. R0A 5-to-32 decoder R31B R0B LR31 RCE R31A R31 RBE R0C RAE This part will be repeated for R2BUS as shown on the next slide BUS2R

Alternate control circuitry for register select (continued…) ….. IR opc ra rb rc Repeat 32 times 5 R0out R1out R31out R2BUS ….. R0 R1 R31 R0A R0C R0B 5 R0C X 5 R1C R0B ….. R1B 5-to-32 decoder R0A ….. ….. R1A 5-to-32 decoder R31C ….. 5-to-32 decoder R31B RCE R31A RBE RAE

Control signals for the add instruction Syntax: add ra, rb, rc Step RTN Control Signals T0 – T2 Instruction Fetch As before T3 A R[rb]; RBE, R2BUS, LA T4 C A+R[rc]; RCE, R2BUS, ADD, LC T5 R[ra] C; Cout’ RAE, BUS2R

How to perform sign extension? ….. ….. 31 … 16 IR c2 Bus<16..0> 17 Tri-state buffers 17 17 Enable Bus<31..17> 1 15 Tri-state buffers 15 … Enable Sign extension of the 22 bit constant c1 will be done in the same way c2out

Structural RTL for the addi instruction Syntax: addi ra, rb, c2 Step RTL for addi Control signals T0-T2 Instruction fetch As before T3 A R[rb]; RBE, R2BUS, LA T4 C A + c2(sign extend); c2out, ADD, LC T5 R[ra] C; Cout’ RAE, BUS2R

How to place a 0 on the bus when rb=0 in a ld or st instruction? ….. 31…27 26…22 21…17 16…12 11 IR Op ra rb rc 5 5 5 RCE To internal bus Tri-state buffers RAE Hardwired to Logic 0 R0out Enable R0 5 5-to-32 decoder R1out ZR2BUS RBE R1 ….. R31out R31 Don’t connect this line to the tri-state buffer at the output of R0 R2BUS RBE

….. For the alternate circuitry 5 R0B R1B R31B RBE How to place a 0 on the bus when rb=0 in a ld or st instruction? For the alternate circuitry Tri-state buffers From IR<21..17> Hardwired to Logic 0 To internal bus 5 Enable R0B R1B ZR2BUS 5-to-32 decoder ….. R31B Instead of connecting this line to the input of the gates, connect it to the enable of the tri-state buffers as shown here RBE

Control signals for the st instruction Syntax: st ra, c2(rb) Step RTL for st Control Signals T0-T2 Instruction fetch As before T3 A ((rb = 0): 0, (rb ≠ 0): R[rb]); RBE, R2BUS, BAout, LA T4 C A + (16αIR<16> ©IR<15..0>); C2out, ADD, LC T5 MAR C; Cout, LMAR T6 MBR R [ra]; RAE, R2BUS, INT2MBR, LMBR T7 M[MAR] MBR; MARout, MWrite

Control signals for the ld instruction Syntax: ld ra, c2(rb) Step RTL for Id Control Signals T0-T2 Instruction fetch As before T3 A ((rb = 0) : 0, (rb ≠ 0): R[rb]); RBE, R2BUS, LA T4 C A + (16αIR<16> ©IR<15..0>); C2out, ADD, LC T5 MAR C; Cout, LMAR T6 MBR M[MAR]; MARout, MRead, LMBR T7 R[ra] MBR; MBRout, RAE, BUS2R

Register Connections