Flip-Flops SHAH KEVAL EN. NO.: 130270111006 EC DEPARTMENT, KIT, JAMNAGAR.

Level-Sensitive Flip-Flop Level-sensitive flip-flop (also called a “latch”) “Q” changes whenever clock is “high” CLK D Q 6 Transistors CLK CLK D Q

Level-Sensitive Flip-Flop CLK D Q NMOS transistor often replaced with “transmission gate” “Transmission gate” includes both NMOS and PMOS transistors because NMOS good at passing “0” and PMOS good at passing “1” 6 Transistors CLK D Q CLK Transmission Gate 8 Transistors CLK

Master-Slave Edge-Triggered Flip-Flop Can connect two level-sensitive latches in Master-Slave configuration to form edge-triggered flip-flop Master latch “catches” value of “D” at “QM” when CLK is low Slave latch causes “Q” to change only at rising edge of CLK QM Master Latch Slave Latch D Q CLK 2 x 8 = 16 Transistors CLK CLK D QM Q

Master-Slave Edge-Triggered Flip-Flop QM D Q CLK CLK 2 x 8 = 16 Transistors

More Efficient Master-Slave Edge-Triggered Flip-Flop Called a C2MOS (Clocked CMOS) design MASTER SLAVE VDD VDD CLK CLK D Q CLK CLK 8 Transistors GND GND

Using Logic Gates to Build Flip-Flops From previous slides, you can see that it’s possible to build an edge-triggered flip-flop using just 8 transistors In a conventional “Digital Logic” course, transistor-level flip-flop designs are not usually taught Instead, flip-flop designs using “cross-coupled” logic gates are usually taught

RS-Latch as Cross-Coupled NOR Gates If R = 1, Q resets to 0 If S = 1, Q sets to 1 If RS = 00, no change RS = 11 is not allowed because leads to oscillation R Q Q S S R Q 0 0 No change 0 1 1 0 1 1 1 Undefined

Level-Sensitive RS-Latch “Q” only changes when CLK is high (i.e. level-sensitive) When CLK is high, behavior same as RS latch S Q CLK Q R CLK S R Q 0 X X No change 1 0 0 No change 1 0 1 1 1 0 1 1 1 1 Undefined

Level-Sensitive D-Latch Make level-sensitive D-latch from level-sensitive RS-latch by connecting S = D and R = not D Compared to transistor version D Q CLK Q 18 Transistors CLK D Q 8 Transistors

Master-Slave Edge-Triggered Flip-Flop Master-Slave configuration Compared to transistor version MASTER SLAVE D Q CLK CLK 36 Transistors VDD VDD CLK CLK D Q CLK CLK 8 Transistors GND GND

Alternative Edge-Triggered Flip-Flop VDD VDD CLK CLK Q D Q CLK CLK CLK Q GND GND D 24 Transistors 8 Transistors

JK Flip-Flop from D-Latch Same as RS-Latch except “toggle” on 11 J D Latch Q K Q CLK JK-FF J Q CLK J K Q 0 X X No change CLK 1 0 0 No change K 1 0 1 1 1 0 1 1 1 1 Toggle

Toggle Flip-Flop from D-Latch Toggles stored value if T = 1 when CLK is high D Latch Q T CLK CLK T Q T T-FF Q 0 X No change 1 0 No change CLK 1 1 Toggle