NSW Electronics workshop, November 2013 Companion ASICs overview NSW Electronics workshop November 2013 L. Levinson Weizmann Institute L. Levinson NSW Electronics workshop, November 2013

Four companion variants Each variant uses several “components” from a shared set We should make these components easily pluggable. Delay, PLL, E-link components may be available from CERN micro-electronics group Not necessarily four actual packages. Optimize cutting the die, package design. For details: https://twiki.cern.ch/twiki/pub/Atlas/NSWelectronics/CompChipComponents.xlsx   components needed Companion variant alias which FE board num pins clock gen & clock dist TTC distrib pgmable delays TMR config reg file VMM readout on Lvl-1 GBT e-link interface VMM Config MM ART sTGC pad TDS sTGC strip TDS MM ART encoder "IC1" medium √ MM readout "IC2" all MM FE ? sTGC strips, “TDS” strip TDS sTGC FE strip many sTGC pads, “TDS” pad TDS sTGC FE pad L. Levinson NSW Electronics workshop, November 2013

Description of each component L. Levinson NSW Electronics workshop, November 2013

NSW Electronics workshop, November 2013 Companions The companion ASICs are the highest risk items in the NSW electronics (they are ASICs) Not much time (or money) for re-spins We must do all we can to limit the risk by: As simple as possible, but not too simple Reuse designs from other projects Need a “Plan B” (and “C”) To be discussed today, after presentations of each component module “Plan C”: A promising, but as yet unproven, possibility is the IGLOO2 flash-based FPGA from Microsemi (was Actel) An FPGA would enormously reduce risk (and cost) https://twiki.cern.ch/twiki/pub/Atlas/NSWelectronics/IGLOO2CustomerWebinar.pdf L. Levinson NSW Electronics workshop, November 2013

NSW Electronics workshop, November 2013 IGLOO2 Flash-based FPGA  low power (IGLOO) Four 5G serializers 65nm  expect good TID radiation tolerance Microsemi says “SEU immune configuration”, “SEU immune serializers” Microsemi is measuring their rad tolerance They sell older flash and anti-fuse FPGAs that are radtol to some extent L. Levinson NSW Electronics workshop, November 2013

NSW Electronics workshop, November 2013 Readout component Interfaces between VMM and GBT Uncertain how to divide, between VMM and readout companion, the task of buffering data until Level-1 Accept and preparing it for transmission BW needed for VMM to send all hits to companion for buffering is probably too high, especially for sTGC (sTGC strip = 3.2/0.5 = ~6.4 times area of a MM strip) To be discussed in readout session No one has yet taken responsibility for this component A working group to be formed to define the specifications L. Levinson NSW Electronics workshop, November 2013

TMR register file for configuration registers All modules need an SEU-hardened register file for configuration registers This is another shared module. Suggest registers written by SCA chip, i.e. via I2C (take design from VMM) If not, this component should use same data format from E-link as SCA so that same configuration SW can be used. No one has yet taken responsibility for this component L. Levinson NSW Electronics workshop, November 2013

NSW Electronics workshop, November 2013 TTC, delays and clock module for the companion ASICs NSW Electronics workshop November 2013 L. Levinson Weizmann Institute L. Levinson NSW Electronics workshop, November 2013

NSW Electronics workshop, November 2013 Functions performed Provide BC and other clocks for the VMM and the other companion modules with configurable delays. Clock gen & clock distribution: The VMM & other companion modules require 40MHz, 80MHz, 160MHz clocks. These must be generated from either from an e-link clock or a programmable 40MHz clock from the GBT. TTC distribution: The Level-1 readout requires BCR, L1Accept, ECR. Also required: test-pulse, board reset. These must be decoded from a TTC e-link stream and sent to all VMMs. Decode the TTC signals from the two 40Mb/s TTC E-link bits. Programmable delays: The clocks and TTC signals must have programmable delays to compensate for Companion and VMM chips being at different distances from their GBT chip. L. Levinson NSW Electronics workshop, November 2013

Open issues for TTC & clocks Choose between 80MHz E-link clock, or one of the 40MHz GBT output clocks GBT clocks have configurable delays We need the E-link clocks anyway Unclear how to get the correct phase of BC from the 80MHz E-link clock What can we get from CERN Micro-electronics? TTC A-channel (= L1A) and B-channel (= cmds) decoder from GLIB project. FELIX could decode raw B-channel into a more friendly serial packet (HDLC) for ECR, BCR, TP, board reset PLL: this is the highest risk item: stability and jitter for serializers Programmable delay L. Levinson NSW Electronics workshop, November 2013