Single Clock Datapath With Control Morgan Kaufmann Publishers 12 September, 2018 Single Clock Datapath With Control Chapter 4 — The Processor — 2 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 MIPS Pipeline Five stages, one step per stage IF: Instruction fetch from memory ID: Instruction decode & register read EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register Chapter 4 — The Processor — 3 Chapter 4 — The Processor

MIPS Pipelined Datapath Morgan Kaufmann Publishers 12 September, 2018 MIPS Pipelined Datapath Chapter 4 — The Processor — 4 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 Pipeline registers Need registers between stages To hold information produced in previous cycle IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 5 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 IF for Load, Store, … IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 6 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 ID for Load, Store, … IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 7 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 EX for Load IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 8 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 MEM for Load IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 9 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 WB for Load Wrong register number IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 10 Chapter 4 — The Processor

Corrected Datapath for Load Morgan Kaufmann Publishers 12 September, 2018 Corrected Datapath for Load IF/ID ID/EX EX/MEM MEM/WB Chapter 4 — The Processor — 11 Chapter 4 — The Processor

Single-Cycle Pipeline Diagram Morgan Kaufmann Publishers 12 September, 2018 Single-Cycle Pipeline Diagram State of pipeline in a given cycle Chapter 4 — The Processor — 12 Chapter 4 — The Processor

Pipelining and ISA Design Morgan Kaufmann Publishers 12 September, 2018 Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing Can calculate address in 3rd stage, access memory in 4th stage Alignment of memory operands Memory access takes only one cycle Chapter 4 — The Processor — 13 Chapter 4 — The Processor

Pipeline Hazards Situations occur when the next instruction cannot be overlapped

Pipeline Hazards Situations occur when the next instruction cannot be overlapped Structural Hazards occur when the hardware cannot support the combination of instructions

Pipeline Hazards Situations occur when the next instruction cannot be overlapped Structural Hazards occur when the hardware cannot support the combination of instructions Control Hazards occur when a decision needs to be made while others are executing - a branch instruction

Pipeline Hazards Situations occur when the next instruction cannot be overlapped Structural Hazards occur when the hardware cannot support the combination of instructions Control Hazards occur when a decision needs to be made while others are executing - a branch instruction Data Hazards occur when an instruction depends on the results of a previous instruction still in the pipeline.

Structural Hazards occur when the hardware cannot support the combination of instructions 1. Design ISA for pipelining 2. Stall to clear - DELAY

Multi-Cycle Pipeline Diagram Morgan Kaufmann Publishers 12 September, 2018 Multi-Cycle Pipeline Diagram Form showing resource usage Write Reg first half – Read Reg second half Chapter 4 — The Processor

MIPS Pipelined Datapath Morgan Kaufmann Publishers 12 September, 2018 MIPS Pipelined Datapath MEM Right-to-left flow leads to hazards WB Chapter 4 — The Processor — 20 Chapter 4 — The Processor

Control Hazards occur when a decision needs to be made while others are executing - a branch instruction 1. Stall until branch can be resolved Some compilers can fill the delays with useful instructions.

Control Hazards occur when a decision needs to be made while others are executing - a branch instruction 1. Stall until branch can be resolved Some compilers can fill the delays with useful instructions. 2. Predict the branch decision. If correct, then full speed If wrong, nullify instructions following the wrong branch and restart the pipeline at the correct address

MIPS Pipelined Datapath Morgan Kaufmann Publishers 12 September, 2018 MIPS Pipelined Datapath MEM Right-to-left flow leads to hazards WB Chapter 4 — The Processor — 23 Chapter 4 — The Processor

Morgan Kaufmann Publishers 12 September, 2018 Data Hazards An instruction depends on completion of data access by a previous instruction add $s0, $t0, $t1 sub $t2, $s0, $t3 STALL Chapter 4 — The Processor — 24 Chapter 4 — The Processor

Data Hazards occur when an instruction depends on the results of a previous instruction still in the pipeline. 1. Stall 2. Reorder 3. Forwarding combined with stall and reorder

Forwarding (aka Bypassing) Morgan Kaufmann Publishers 12 September, 2018 Forwarding (aka Bypassing) Use result when it is computed Don’t wait for it to be stored in a register Requires extra connections in the datapath Chapter 4 — The Processor — 26 Chapter 4 — The Processor

Code Scheduling to Avoid Stalls Morgan Kaufmann Publishers 12 September, 2018 Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall 13 cycles 11 cycles Chapter 4 — The Processor — 27 Chapter 4 — The Processor