EKT 121 / 4 DIGITAL ELECTRONICS I Chapter 3: Sequential Logic Circuits

“Combinational” vs “Sequential” Combinational – outputs depend only on the inputs. Do not have memory. Cannot store state. Sequential – outputs depend on inputs and past behavior. Require use of storage elements. Contents of storage elements is called “state”. Circuit goes through sequence of states as a result of changes in inputs.

Overview of Sequential Circuits Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams

Introduction to Sequential Circuits Inputs Outputs Combina-tional Logic A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinatorial Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Storage Elements State Next State

Block Diagram of a Sequential Circuit

Sequential Circuit Behaviour Is determined from the inputs, outputs and present state. The outputs and the next state are a function of the inputs and the present state.

Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable!

Synchronous Clocked Sequential Circuit

Sequential Circuit - Basic Function The data stored in the “storage elements” defines the “state” of the sequential circuit at that time, i.e. present state. The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.

Simple Memory Structure

Another Structure for Memory Reset Set Q

The Most Common Memory Elements Used Latches Flip-flops The basic single-bit memory elements, With one or two inputs/outputs, Designed using individual logic gates and feedback loops. Both are referred to as “bistable elements” or “multivibrator”, i.e. having two stable states.

Latch vs Flip-flop Latch Asynchronous. “The inputs, together with the present state of the storage elements, determine the outputs and the next state of the storage elements.” Latch Asynchronous. Change of state can happen at any time, whenever its inputs change. Flip-Flops Synchronous. Change of state occurs only at specific times determined by a clock pulse input. Flip-flops are constructed from latches!!

Types of Latches SR Latch Gated D Latch S R Latch Q C R Gated SR Latch (with control)

S R Latch

SR Latch with NOR Gates Q Reset Set Q Re-drawn …

The SR Latch Operation Cross-coupling two NOR gates gives the S – R Latch: Which has the time sequence behavior: S (set) R (reset) Q R S Q Comment ? Stored state unknown 1 “Set” Q to 1 Now Q “remembers” 1 “Reset” Q to 0 Now Q “remembers” 0 Both go low Unstable! Time If Q=1, NQ=0 => SET state If Q=0, NQ=1 => reSET state

SR Latch Operation If Q=1, NQ=0 => SET state If Q=0, NQ=1 => reSET state Under normal conditions, S=R=0, unless the state is to be changed. S=1 and R=0 => SET (1) state. The S input must go back to 0 before R is changed to 1, to avoid occurrence of the undefined state (S=R=1). The same goes when applying S=0 and R=1.

SR Latch Function Table Hold Hold

… SR Latch Operation If S=R=0 => the latch is either SET or reSET.. If S=R=1 => both Q and NQ = 0. Undefined State!! … violation of Q vs NQ.

Simulation of SR Latch .. with delay

S-R Latch vs S-R Latch

S R Latch

S R Latch with NAND Gates Q Active-LOW SR Latch …

The S–R Latch Operation “Cross-Coupling” two NAND gates gives the S -R Latch: Which has the time sequence behavior: S = 0, R = 0 is forbidden as input pattern S (set) Q Q R (reset) Time R S Q Comment 1 ? Stored state unknown “Set” Q to 1 Now Q “remembers” 1 “Reset” Q to 0 1 1 1 Now Q “remembers” 0 1 1 Both go high 1 1 ? ? Unstable!

SR Latch Function Table Hold Hold

S R Latch Function Table

S R Latch Waveform 1 2 3 4 5 6 7 Assume that Q is initially LOW

Gated SR Latch = SR latch with Control input Q C R C or Enable or CLock = SR latch with Control input = SR latch with Enable input = Clocked SR Latch

Gated S-R Latch - Basic Operation A gate input is added to the S-R latch to: - Act as a “control” input. Make the latch synchronous. Control=1 => Latch can change state Control =0 => Latch “holds” previous value

Gated SR Latch Function Table Where is the additional circuit?

Gated SR Latch Operation The table describes what happens after the clock [at time (t+1)] based on: current inputs (S,R) and current state Q(t). S R Q C

Gated SR Latch Simulation Q C R R C Q S 1 Time ?

Gated D Latch D Q C

Gated D Latch Add inverter to the SR latch…

Gated D Latch Function Table Note: There are no “indeterminate states” …

Gated D Latch Simulation 1 2 3 4 Time Clk D Q

State Change in Latch Change in latch state => Trigger The D latch with clock pulses on its Control, C, input is triggered every time a pulse to logic-1 level occurs. As long as the pulse remains at the logic-1 level, any changes in the data input will change the state of the latch. “Level” triggered

The Latch Timing Problem Consider the following circuit: Suppose that initially Y = 0. As long as C = 1, the value of Y continues to change! The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse C D Q Y Clock Clock Y

Solution to the Latch Timing Problem – Use latch to form flip-flop Replace the clocked D-latch with: A Master-slave Flip-flop Two stage Output does not change until clock is disabled An Edge-triggered Flip-flop Triggers only during a signal transition on the clock, either from 1 to 0 or from 0 to 1, and is disabled at all other times.

Master-Slave Flip-flops SR JK D

Master-Slave Flip-flop Symbols

Master-Slave Flip-flops Is pulse (level)-triggered. Data is entered into the flip-flop at the leading edge of the clock pulses, but the output is only reflected at the trailing edge. Does not allow data to change while the clock pulse is still active. …. Either the Master or the Slave is enabled, not both

Master-Slave SR Flip-Flop

Master-Slave SR Flip-Flop When C=0, the output of the inverter is 1 => the slave latch is enabled, and its output, Q, is equal to the master output, Y. The master latch is disabled because C=0. When a logic-1 pulse is applied to C, the values on S and R control the stored value in the master latch, Y. The slave at this time is disabled, because its C input is 0. Any changes in the S and R inputs change the master output, Y, but cannot affect the slave output, Q. When the pulse returns to 0, the master is disabled and is isolated from the S and R inputs. At the same time, the slave is enabled, and the current value of Y is transferred to the output of the flip-flop at Q.

Master-Slave SR Flip-Flop Consists of two clocked SR latches in series with the clock on the second latch inverted. The input is observed by the first latch with C = 1. The output is changed by the second latch with C = 0. The path from input to output is broken by the difference in clocking values (C = 1 and C = 0). The behavior demonstrated by the example with D driven by Y given previously is prevented since the clock must change from 1 to 0 before a change in Y based on D can occur. C S R Q

Simulation of an Master-Slave SR Flip-Flop

Master-Slave JK Flip-Flop Hold Look for similarity/ difference with SR… Reset Set Toggle (Opposite State)

Master-slave JK flip-flop. (a) Logic diagram using gated SR latches Master-slave JK flip-flop. (a) Logic diagram using gated SR latches. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

Timing diagram for master-slave JK flip-flop

Master-Slave D Flip-Flop Q Master Slave Clock m s C D Clock Q m s = Timing diagram

Master-slave T Flip-flop

Flip-Flop Problem The change in the flip-flop output is delayed by the pulse width which makes the circuit slower or S and/or R are permitted to change while C = 1 Suppose Q = 0 and S goes to 1 and then back to 0 with R remaining at 0 The master latch sets to 1 A 1 is transferred to the slave Suppose Q = 0 and S goes to 1 and back to 0 and R goes to 1 and back to 0 The master latch sets and then resets A 0 is transferred to the slave This behavior is called 1s catching

Flip-Flop Solution Use edge-triggering instead of master-slave. An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal. Edge-triggered flip-flops can be built directly at the electronic circuit level, or A master-slave D flip-flop which also exhibits edge-triggered behavior can be used.

Edge-Triggered Flip-flops Flip-flops are synchronous bistable devices. Synchronous: because the output changes state ony at a certain point on a triggering input, i.e. CLK, which is the control input. Edge-triggered flip-flop: changes state at either the positive edge (rising edge) or at the negative edge (falling edge) of the cock pulse.

Clock Signals & Synchronous Sequential Circuits Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signal Clock Cycle Time 1 A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

Edge-triggered Flip-flop Symbols Positive edge triggered and Negative edge-triggered All the above flip-flops have the triggering input called clock (CLK/C)

Edge-Triggered Flip-flops SR flip-flop JK flip-flop D flip-flop T flip-flop

Timing Diagram

Negative-Edge Triggered D Flip-Flop The edge-triggered D flip-flop is the same as the master- slave D flip-flop. It can be formed by: Replacing the first clocked S-R latch with a clocked D latch or Adding a D input and inverter to a master-slave S-R flip-flop The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs The change of the D flip-flop output is associated with the negative edge at the end of the pulse. It is called a negative-edge triggered flip-flop C S R Q D

Positive-Edge Triggered D Flip-Flop Formed by adding inverter to clock input Q changes to the value on D applied at the positive clock edge within timing constraints to be specified. The standard flip-flop used for most sequential circuits. C S R Q D D Q Clock

Positive-Edge-Triggered D Flip-Flop 1 P3 P1 2 5 Q Clock D Q (b) Graphical symbol Clock P2 6 Q 3 4 P4 D (a) Circuit

A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter D CLK/C Q Q’_________________ 1 ↑ 1 0 SET (stores a 1) 0 ↑ 0 1 RESET (stores a 0)

Timing Diagram

Positive-Edge Triggered JK Flip-Flop Not used much anymore in VLSI Advantageous only if using FF chips A real case of “learning the hard stuff just because the lecturer wants to make things hard for you” J D Q Q K Q Q Clock (a) Circuit J K Q ( t + 1 ) Q ( t ) J Q 1 1 1 K Q 1 1 Q ( t ) (b) Truth table (c) Graphical symbol

Function Table for JK Flip Flop J K CLK Q Q’ 0 0 Q0 Q0’ Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 Q0’ Q0 Toggle (opposite state)

Timing Diagram: Positive-Edge Triggered

Timing Diagram: Negative-Edge Triggered

T Flip-Flop Useful in counters Not available in IC form T Latches do not exist T Q ( t + 1 ) Q ( t ) 1 Q ( t ) (b) Truth table D Q T Clock (a) Circuit T Q Q (c) Graphical symbol

T Flip-Flop Clock T Q (d) Timing diagram

D latch vs D flip-flop

D Latch versus D Flip-Flop Q Q a D Clock Q a b c Clock Clk Q Q a D Q Q b Q Q b D Q Q c Q Q c (a) Circuit (b) Timing diagram Comparison of level-sensitive and edge-triggered devices

Standard Graphic Symbols for Latch and Flip-Flops Complete the list !! T T

Direct Inputs Preset (Set) & Clear (ReSet)

Clear and Preset Inputs Set/Reset independent of clock Direct set or preset Direct reset or clear Often used for power-up reset Preset Q Preset Clock D Q Q Q Clear D (b) Graphical symbol Clear (a) Circuit

Example: D-FF with Direct Set and Reset

Direct Inputs At power up or at reset, all or part of a sequential circuit usually is initialized to a known state before it begins operation This initialization is often done outside of the clocked behavior of the circuit, i.e., asynchronously. Direct R and/or S inputs that control the state of the latches within the flip-flops are used for this initialization. For the example flip-flop shown 0 applied to R resets the flip-flop to the 0 state 0 applied to S sets the flip-flop to the 1 state D C S R Q

J-K flip-flop with active-LOW Preset and Clear inputs

Timing Diagram

State Diagram, Excitation Table, Characteristic Equation

Detailed Function Table SR Latch SR 1 SR 0X 10 X0 01 00 01 11 10 X 1 Q Detailed Function Table S R Q Q+ 1 X Characteristic Equation: Q+ = S + R’Q Excitation Table Q Q+ S R X 1 State Transition Diagram: The excitation table in graphical form Excitation Table: What are the necessary inputs to cause a particular kind of change in state?

Detailed Function Table D Latch D 1 1 Q Detailed Function Table D Q Q+ 1 Characteristic Equation Q+ = D Excitation Table Q Q+ D 1 State Transition Diagram

Detailed Function Table JK Flip-Flop 00 01 11 10 1 JK 1 JK 0X 1X X0 X1 Q Detailed Function Table J K Q Q+ 1 Characteristic Equation Q+ = JQ’ + K’Q Excitation Table Q Q+ J K X 1 State Transition Diagram

Detailed Function Table T Flip-Flop T 1 1 Q Detailed Function Table T Q Q+ 1 Characteristic Equation Q+ = T’Q + TQ’ = T  Q Excitation Table Q Q+ D 1 State Transition Diagram

Choosing a Flip-Flop SR Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, is the fundamental building block of other flip-flop types D Flip-flop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers JK Flip-flop: versatile building block: can be used to implement D and T FFs usually requires least amount of logic to control Q+ however, has two inputs with increased wiring complexity T Flip-flop: doesn't really exist, constructed from J-K FFs usually best choice for implementing counters Preset and Clear inputs highly desirable!!

Characteristic Equation & Excitation Table Summary Device Type Characteristic Equation SR latch Q+ = S + R’Q D latch Q+ = D JK flip-flop Q+ = JQ’ + K’Q T flip-flop Q+ = TQ’ + T’Q Q Q+ S R D J K T X 1

Flip-flop Applications Parallel Data Storing Frequency Divider Counter

Parallel Data Storing –using Registers 4-bit REGISTER

Frequency Divider: Divide-by-2 Q is one-half the frequency of CLK

Frequency Divider: Divide-by-4

Counter : 00, 01, 10, 11 2-bit Counter

SEQUENTIAL CIRCUITS Design Examples Using Flip-flops

Example 1 Input: x(t) Output: y(t) State: (A(t), B(t)) What is the Output Function? What is the Next State Function? A C D Q y x B CP

Example 1 Boolean equations for the functions: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A(t)x(t) y(t) = x(t)(B(t) + A(t)) x D Q A C Q A Next State D Q B CP C Q' y Output

State Table Characteristics State table – a multiple variable table with the following four sections: Present State – the values of the state variables for each allowed state. Input – the input combinations allowed. Next-state – the value of the state at time (t+1) based on the present state and the input. Output – the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present State and the outputs are Output, Next State

Example 1: State Table The state table can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 1 1

Example 1: Alternate State Table 2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Present State Next State x(t)=0 x(t)=1 Output x(t)=0 x(t)=1 A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0

State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input values which causes the state transition, and A label: On each circle with the output value produced, or On each directed arc with the output value produced.

State Diagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input

Example 1: State Diagram A B 0 0 0 1 1 1 1 0 x=0/y=1 x=1/y=0 x=0/y=0 Which type? Diagram gets confusing for large circuits For small circuits, usually easier to understand than the state table Type: Mealy

Standard Graphic Symbols for Latch and Flip-Flops

Flip-Flop Characteristic Table

Flip-Flop Excitation Tables

Examples Using D-Flip-flop

Example 1 D-Flip-flop

From State Table  Derive Equation Q(t) Q(t+1)

Then.. Produce the Schematic

Example 2 D-Flip-flop

State table for Circuit of Fig 4.18

The Flip-flop Input Equations DA = (AX +BX) Equations for FF inputs DB = A.X Y = ( A+B ) . X - Equation for output Y Subscripts A and B: names of FF outputs.

How to derive the flip-flop output equations as well as for output Y?

Two-Dimensional State Table for the Circuit in Figure 4.18

Example 2: D Flip-flop Design DA = (AX +BX) DB = A.X Y = ( A+B ) . X

Example 3 D-Flip-flop

State Diagram for Design Example

State Table for Design Example

Maps for Input Equations and Output Y

Logic Diagram for Sequential Circuit with D Flip-Flops

Example 4 D-Flip-flop

State Table

Maps for Simplifying Input Equations

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