Spartan FPGAs مرتضي صاحب الزماني.

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Presentation transcript:

Spartan FPGAs مرتضي صاحب الزماني

Xilinx Spartan FPGA SRAM-based مرتضي صاحب الزماني

Xilinx Spartan FPGA SRAM-based مرتضي صاحب الزماني

Xilinx FPGAs مرتضي صاحب الزماني

مرتضي صاحب الزماني Spartan-6 Artix-7 Kintex-7 Virtex-7 Spartan-6 Artix-7 Kintex-7 Virtex-7 Kintex UltraScale Virtex UltraScale Logic Cells 147,443 215,360 477, 760 1,954,560 1,160,880 4,407,480 BlockRAM 4.8Mb 13Mb 34Mb 68Mb 76Mb 115Mb DSP Slices 180 740 1,920 3,600 5,520 2,880 Transceiver Count 8 16 32 96 64 104 Transceiver Speed 3.2 Gb/s 6.6 Gb/s 12.5 Gb/s 28.05 Gb/s 16.3 Gb/s 32.75 Gb/s Total Transceiver Bandwidth (full duplex) 50 Gb/s 211 Gb/s 800 Gb/s 2,784 Gb/s 2,086 Gb/s 5,101 Gb/s I/O Pins 576 500 1,200 832 1,456 مرتضي صاحب الزماني

CLB Architecture مرتضي صاحب الزماني

Interconnects مرتضي صاحب الزماني

Interconnects مرتضي صاحب الزماني

Spartan-6 CLB مرتضي صاحب الزماني

SliceM مرتضي صاحب الزماني

Slice Architecture For implementing arbitrary logic For distributed memory Single/dual-port RAM For shift register Each slice: 8 FFs/latches مرتضي صاحب الزماني

Memory Block memories: One 18 Kb block Two 9 Kb blocks مرتضي صاحب الزماني

Block Memory Configurations مرتضي صاحب الزماني

Spartan 6 Characteristics مرتضي صاحب الزماني

Memory: Applied Notes Designer can use distributed or block RAM for memory implementation If memory width > 16 bits  has to use block RAM If needs asynchronous read  has to use distributed RAM But may lead to shortage of LUTs for logic مرتضي صاحب الزماني

DSP Blocks مرتضي صاحب الزماني

DSP Blocks 18 x 18-bit multiplier 48-bit accumulator Can do Multiply-Accumulate (MAC operation) Registers: for synchronization with clock Can do pipelining If need to add two values before multiplication, use pre-adder مرتضي صاحب الزماني

Spartan 6 Characteristics مرتضي صاحب الزماني

IO Blocks Like many other FPGA chips Register or not register High-Z capability and pull-up/down Slew rate control مرتضي صاحب الزماني

Clock Management Tiles CMT Blocks Reduced skew Jitter removal Frequency: n . f or n/2 . f (n ∈ [1, 16]) f/n (n ∈ [1, 128]) Phase shift: 45, 90, 135, …, 315 مرتضي صاحب الزماني

Gigabit Transceiver High-throughput transmit/receive Pre-emphasis Equalization 614 Mb/s to 3.125 Gb/s مرتضي صاحب الزماني

Spartan 6 مرتضي صاحب الزماني

Virtex Very similar architecture More hardware resources 36 Kb Block RAMs PowerPC in Virtex II-Pro, Virtex-4 and Virtex-5 ARM Cortex-9 in Zync-7000 مرتضي صاحب الزماني

مرتضي صاحب الزماني Spartan-6 Artix-7 Kintex-7 Virtex-7 Spartan-6 Artix-7 Kintex-7 Virtex-7 Kintex UltraScale Virtex UltraScale Logic Cells 147,443 215,360 477, 760 1,954,560 1,160,880 4,407,480 BlockRAM 4.8Mb 13Mb 34Mb 68Mb 76Mb 115Mb DSP Slices 180 740 1,920 3,600 5,520 2,880 Transceiver Count 8 16 32 96 64 104 Transceiver Speed 3.2 Gb/s 6.6 Gb/s 12.5 Gb/s 28.05 Gb/s 16.3 Gb/s 32.75 Gb/s Total Transceiver Bandwidth (full duplex) 50 Gb/s 211 Gb/s 800 Gb/s 2,784 Gb/s 2,086 Gb/s 5,101 Gb/s I/O Pins 576 500 1,200 832 1,456 مرتضي صاحب الزماني

Xilinx CoolRunner CPLD مرتضي صاحب الزماني

CoolRunner Functional blocks: AIM (Advanced Interconnect Matrix): Implement logic functions AIM (Advanced Interconnect Matrix): Interconnections between AIMs (and between AIMs and IO blocks) Configuration in flash memory مرتضي صاحب الزماني

AIM Macrocells مرتضي صاحب الزماني

PLA مرتضي صاحب الزماني

IO Blocks Buffering Registering Open-drain structure Pull-up resistor … مرتضي صاحب الزماني