Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao Talk for the 4th PCaPAC International Workshop CERN- EP division, ED Electronics group A.Guirao, F. Bal, M.E. Castro, H.Müller, K. Wyllie, CERN S.Jolly, Imperial College London F.Ballester, UPV Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Contents Introduction to project requirements Minimizing a previous test system What the PC architecture and PCI offer The concept of the new solution Building the real system S-LINK Front-end electronics PCI hardware readout controller Software control interface Performance Conclusions and outlook Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Project Requirements Laboratory test system for LHCb RICH Pixel Chips Test system on-line within 3 months 40MHz clock rate 1MHz event-rate, 32 DWORDs burst per event Inexpensive Flexible functionality Portable and handy– different applications Chip characterisation Wafer testing Module (Photodetector) testing Testbeams Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Minimizing a PIXEL chip test system READOUT CTRLER (CPU) CRATE New solution PCI BUS CTLER I/O DAQ computer DAQ computer READOUT CARD READOUT CARD I/O I/O DETECTOR DETECTOR (PIXEL CHIP) BACKPLANE BUS Solution for the previous version of the pixel chip (10MHz test system) Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

The PC architecture and PCI Advantages: CPUs and many hardware resources available Most common and familiar bus architecture FPGA support Any conventional OS works with the PCI Low cost Partitionable (several controllers per bus) PCI 32b@33MHz, 64b@66MHz, cPCI available Drawbacks: Limited space for electronics Limited power Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Concept of the new solution HARDWARE SOFTWARE PCI APPLICATION LAYER READOUT CONTROLLER I/Os FPGA DLL/module HAL Custom protocol ON-BOARD MEMORY SYSTEM HARDWARE SYSTEM MEMORY HOST BRIDGE CPU Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Building a real system 1 2 Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

S-LINK Front-End electronics Single mode (32 dwords for LHCb) or multievent readout mode (up to 16 events per trigger) Adaptation of S-LINK bus width for LVDS serializers Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

PCI Readout Controller The FLIC card Standard PCI card  small, familiar Easy to use (Plug&Play) General Purpose solution Mezzanine cards interchangeable Custom HW interface (FPGA, HDL) Low cost Large data buffer  local memory becomes system memory FPGA LOGIC Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Readout Software LabView Analysis and Interface Existing analysis software for the chip Interface with commercial cards (JTAG controller) Need of developing a WindowsTM driver for the FLIC Existing support for Linux Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Performance LHCb pixel mode 40MHz clock 32 dwords burst 32b@33MHz 132MB/s payload FLIC input 64b@16MHz 132MB/s SDRAM 64MB MEMORY BANKS DATA SOURCE SLINK SLINK SLINK 32b@40MHz FLIC PCI 32b@33MHz Jungo driver FLIC specific DLL REAL-TIME OFFLINE HARDWARE LabView interface 3MB/s SOFTWARE Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Conclusions and Future A test system has been built based on PCI controller 40MHz performance reached More systems have been reproduced in short time Low cost per system Works under LabView Logically compatible with the previous test system Easy maintenance and upgrading Future possibilities Scalability: several readout controllers per PC Higher speed in the software domain (DMA engines) More complex controllers may fit in larger FPGAs Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card

Read-out of high-speed S-LINK data via a buffered PCI card Thanks! Guirao - Frascati 2002 Read-out of high-speed S-LINK data via a buffered PCI card