Fredkin/Toffoli Templates for Reversible Logic Synthesis

Slides:



Advertisements
Similar presentations
Reversible Gates in various realization technologies
Advertisements

Realization of Incompletely Specified Reversible Functions Manjith Kumar Ying Wang Natalie Metzger Bala Iyer Marek Perkowski Portland Quantum Logic Group.
SYNTHESIS OF REVERSIBLE CIRCUITS WITH NO ANCILLA BITS FOR LARGE REVERSIBLE FUNCTIONS SPECIFIED WITH BIT EQUATIONS Nouraddin Alhagi, Maher Hawash, Marek.
A Transformation Based Algorithm for Reversible Logic Synthesis D. Michael Miller Dmitri Maslov Gerhard W. Dueck Design Automation Conference, 2003.
Derivatives of Perkowski’s Gate k f2 g h t t De Vos gates  f1f1  A B P Q Feynman gates A B P f 2f 2  C Q R Toffoli gates Q P f 2 A C R B S D 0.
Reversible Computation Computational Group Theory and Circuit Synthesis.
DARPA Scalable Simplification of Reversible Circuits Vivek Shende, Aditya Prasad, Igor Markov, and John Hayes The Univ. of Michigan, EECS.
1 COMP541 Combinational Logic Montek Singh Jan 16, 2007.
Reversible Circuit Synthesis Vivek Shende & Aditya Prasad.
Logic Synthesis 5 Outline –Multi-Level Logic Optimization –Recursive Learning - HANNIBAL Goal –Understand recursive learning –Understand HANNIBAL algorithms.
Introduction to Reversible Ckts Igor Markov University of Michigan Electrical Engineering & Computer Science.
April 25, A Constructive Group Theory based Algorithm for Reversible Logic Synthesis.
Classical and Quantum Circuit Synthesis An Algorithmic Approach.
Minimization Techniques for Reversible Logic Synthesis.
Combinational Logic Design
Quantum Error Correction Jian-Wei Pan Lecture Note 9.
REVERSIBLE LOGIC SYNTHESIS. Overview of the Presentation 1. Introduction 2. Design of a Reversible Full-adder Circuit.
1 Cost Metrics for Reversible and Quantum Logic Synthesis Dmitri Maslov 1 D. Michael Miller 2 1 Dept. of ECE, McGill University 2 Dept. of CS, University.
Combinational Logic 1.
Module 4.  Boolean Algebra is used to simplify the design of digital logic circuits.  The design simplification are based on: Postulates of Boolean.
Digital Electronics Lecture 6 Combinational Logic Circuit Design.
+ CS 325: CS Hardware and Software Organization and Architecture Gates and Boolean Algebra Part 2.
1 A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani {msaeedi, msedighi, aut.ac.ir.
Elements of discrete devices synthesis (module T170M012) 2012 Kaunas university of technology Electronic and measurement systems dep. Doc. dr. Žilvinas.
Weikang Qian. Outline Intersection Pattern and the Problem Motivation Solution 2.
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda Rolf Drechsler Alex Orailoglu Computer Science & Engineering Dept. University.
ELE 523E COMPUTATIONAL NANOELECTRONICS
Generating Toffoli Networks from ESOP Expressions Yasaman Sanaee Winter 2009 University of New Brunswick.
Synthesis of the Optimal 4-bit Reversible Circuits Dmitri Maslov (spkr) University of Waterloo Waterloo, ON, Canada Oleg GolubitskySean Falconer Stanford.
Garbage in Reversible Designs of Multiple Output Functions
CLASSICAL LOGIC SRFPGA layout With I/O pins.
Lecture # 5 University of Tehran
CEC 220 Digital Circuit Design SOP and POS forms Friday, January 23 CEC 220 Digital Circuit Design Slide 1 of 17.
WCCI, Vancouver, Canada July 20, 2006 Level Compaction in Quantum Circuits D. Maslov - University of Waterloo, Canada G. W. Dueck - University of New Brunswick,
Quantum Circuit Simplification Using Templates D. Maslov - University of Victoria, Canada G. W. Dueck - UNB, Canada C. Young - University of Victoria,
Templates for Toffoli Network Synthesis by Dmitri Maslov Gerhard W. Dueck Michael D. Miller.
BDD-based Synthesis of Reversible Logic for Large Functions Robert Wille Rolf Drechsler DAC’09 Presenter: Meng-yen Li.
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
Digital Systems Design 1 Signal Expressions Multiply out: F = ((X + Y)  Z) + (X  Y  Z) = (X  Z) + (Y  Z) + (X  Y  Z)
A Synthesis Method for MVL Reversible Logic by 1 Department of Computer Science, University of Victoria, Canada M. Miller 1, G. Dueck 2, and D. Maslov.
Fundamentals of Logic Design, 7 th editionRoth/Kinney © 2014 Cengage Learning Engineering. All Rights Reserved. 1 Boolean Algebra (continued) UNIT 3.
Reducing Structural Bias in Technology Mapping
Lecture 7 Multi-Level Gate Networks
CHAPTER 7 MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES
SLIDES FOR CHAPTER 15 REDUCTION OF STATE TABLES STATE ASSIGNMENT
The Analysis of Cyclic Circuits with Boolean Satisfiability
Boolean Algebra & De Morgan's Theorems
The minimum cost flow problem
Combinational Logic Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates,
CHAPTER 3 SETS AND BOOLEAN ALGEBRA
TN 221: DIGITAL ELECTRONICS 1
Lecture 14 Reduction of State Tables
Hidden Markov Models Part 2: Algorithms
Optimization Algorithm
Design Example “Date of Birth Problem”
Resolution Proofs for Combinational Equivalence
Homework 2 This homework is the first use of quantum gates. In lectures we learned about the following gates: inverter, Feynman (controlled NOT), Toffoli.
DESIGN OF SEQUENTIAL CIRCUITS
Synthesis and Verification of Finite State Machines
Heuristic Minimization of Two Level Circuits
Automatic Test Pattern Generation
Overview Part 2 – Circuit Optimization
ECE 352 Digital System Fundamentals
COMP541 Combinational Logic - 3
design entry (schematic capture, VHDL, truth table and etc.)
Theorems on Redundancy Identification
Illustrative Example p p Lookup Table for Digits of h g f e ) ( d c b
Fast Min-Register Retiming Through Binary Max-Flow
Sajib Kumar Mitra, Lafifa Jamal and Hafiz Md. Hasan Babu*
Chapter5: Synchronous Sequential Logic – Part 3
Presentation transcript:

Fredkin/Toffoli Templates for Reversible Logic Synthesis by Dmitri Maslov Dmitri Maslov Gerhard Dueck Michael Miller ICCAD, November 11, 2003, San Jose, CA

Outline Synthesis Procedure Basic definitions Synthesis Procedure The Templates (definition, classification, application) Results ICCAD, San Jose, CA November 11, 2003 page 1/20

Basic Definitions Definition. Multiple output Boolean function is called reversible iff: 1. 2. - is a bijection. In reversible logic fan-outs and feed-back conventionally are not allowed, thus any network is a cascade. ICCAD, San Jose, CA November 11, 2003 page 2/20

Basic Definitions … Toffoli type gates NOT Toffoli CNOT (Feynman) Generalized Toffoli Toffoli type gates ICCAD, San Jose, CA November 11, 2003 page 3/20

Basic Definitions Fredkin gates are the controlled SWAPs. Fredkin gates can be effectively simulated by a Toffoli gate and two CNOTs. ICCAD, San Jose, CA November 11, 2003 page 4/20

Synthesis Procedure The Basic Algorithm Assume the function is given in a truth table as a reversible specification. Start creating the cascade from its end: transform the output to the form of the input. Transform the output pattern to the form of input in lexicographical order. While working with the pattern of higher order do not affect patterns with lower order. ICCAD, San Jose, CA November 11, 2003 page 5/20

Synthesis Procedure in 000 001 010 011 100 101 110 111 out 100 110 101 Final circuit 1 ICCAD, San Jose, CA November 11, 2003 page 6/20

Synthesis Procedure Further Improvements Bidirectional modification: while synthesizing a network the gates can be assigned at both sides. Output permutation. Control input reduction: there may be more than one possible assignment of controls. Apply templates. ICCAD, San Jose, CA November 11, 2003 page 7/20

Templates as a Simplification Tool As 3 gates can be rewritten by a sequence of 2, some s gates can be rewritten as a sequence of k gates (k<s). Network simplification approach. preprocessing: find as many rewriting rules as possible. simplify by matching rewriting rules and rewriting the circuit. ICCAD, San Jose, CA November 11, 2003 page 8/20

Templates as a Simplification Tool Problems in such naive approach. The number of rewriting rules is very large: a. For s=3, k=2 and n=3 (number of lines) the number of rewriting rules is 180 (using Toffoli gates only). b. Many rewriting rules are redundant. c. The number of non-redundant rewriting rules only grows exponentially on n. 2. Very often a rewriting can be applied only when certain gates are moved. ICCAD, San Jose, CA November 11, 2003 page 9/20

The Templates: Definition Observation 1. If one has a rewriting rule then the gates in it satisfy equation Observation 2. If we have an identity then for any parameter p, is a valid rewriting rule. Observation 3. If , then ICCAD, San Jose, CA November 11, 2003 page 10/20

The Templates: Definition A size m template is a cascade of m gates which realizes the identity function. Any template of size m should be independent of smaller size templates, i.e. application of smaller templates does not decrease the number of gates in a size m template. Given G0G1…Gm-1, a template of size m, its application for parameter p, is: for ICCAD, San Jose, CA November 11, 2003 page 11/20

The Templates: Definition Example. Template ABCDEFG. p=4. Starting gate B. Direction: backward. F F E E B A G C D G D A C B m2 How many rewriting rules are there in one template? Parameter p: m/2 choices. Starting gate i: m choices. Directions of application: 2 (forward, backward). ICCAD, San Jose, CA November 11, 2003 page 12/20

The Templates: Classification A class of Toffoli-Fredkin templates is defined as an identity with certain conditions on the form of gates in it. Box gate: - Line with the box is either NOT or SWAP. - All the boxes on the same line are of the same type. - If a line with a box has a NOT or a SWAP on it, the box is necessarily substituted with NOT. ICCAD, San Jose, CA November 11, 2003 page 13/20

The Templates: Classification Class 1: duplication deletion. Class 2: passing rule. ICCAD, San Jose, CA November 11, 2003 page 14/20

The Templates: Classification Group: semi-passing Group: link Group: Fredkin definition ICCAD, San Jose, CA November 11, 2003 page 15/20

The Templates: Classification Class 3: main template. Class 4: fttftt template. ICCAD, San Jose, CA November 11, 2003 page 16/20

The Templates: Application In a program realization: use size 4 templates to move gates – moving rule. Semi-passing templates are used to pass the gate that does not change. for other templates apply smaller templates first (in a sense, smaller template does a more general transformation). - given a template, match it by trying both directions, starting with any gate and trying to move other gates by the moving rule. ICCAD, San Jose, CA November 11, 2003 page 17/20

The Templates: Application ICCAD, San Jose, CA November 11, 2003 page 18/20

The Templates: Application semi-passing passing ICCAD, San Jose, CA November 11, 2003 page 18/20

Results j optimal synthesized 1 18 2 184 3 1318 1290 4 6474 5680 5 17695 13209 6 14134 13914 7 496 5503 8 512 9 WA: 5.134 5.437 Number of reversible functions of size 3 using a specified number of Toffoli-Fredkin gates. More than 77% of synthesized functions are optimal. Average gate count of the synthesized Toffoli-Fredkin circuit is less than optimal gate count for Toffoli network. ICCAD, San Jose, CA November 11, 2003 page 19/20

Benchmark synthesis results Name Size* Number of gates rd32 4 4T rd53 7 12T mod5 5 9T hwb5 24F hwb6 6 65F hwb7 166F ham3 3 4FT ham7 24T ham15 15 138T * - when the function is not reversible, it was synthesized in its minimal reversible specification. ICCAD, San Jose, CA November 11, 2003 page 20/20

END Fredkin/Toffoli Templates for Reversible Logic Synthesis Thanks for Your attention!