Sheng-Li Liu, James Pinfold. University of Alberta HPTDC DEVELOPMENT Sheng-Li Liu, James Pinfold. University of Alberta

QUARTIC 8 Channel TDC Board Prototype (Rev. 1.1 Shengli, Jan. 21/08 Input to the HPTDC board from ACFD (includes amp. + precision CFD). ACFD Standalone board with 8 diff. LVPECL chnnls for rms res. ~ 20 ps. It has: 1 HPTDC Chip (V1.3) working in very high resolution mode. An ALTERA FPGA Serial LVDS link to connect to the main RODs, for the beam test data taking. Normally the Serial LVDS link will provide all the timing & control signals to HPTDC, i.e. 40 MHz clock, bunch & event reset, conduct config. to HPTDC through JTAG interface, and take data, send and read configuration data to and from the FPGA.

FPGA Block Diagram Rev 1.1, Shengli, January 21, 2008 The FPGA will: Control the readout from the HPTDC in parallel 32bit, Perform the Integral Non-linear Compensation by Look Up Table, After it builds the event according to some rules, it will guide the data to go either optic link or USB. The FPGA will also take all the commands from the optic link or USB and maintain a stack of registers. Another important task for FPGA is the JTAG programming support. This programming information could either take USB path or ROD’s path.

Schedule to Beam Tests Schedule for development: January to Feb 2008: Development of Schematics and PCB, FPGA coding/Simulation March: PCB assembly April to May: FPGA coding, TDC Programming and DLL, RC Parameter adjusting June to July: Performance testing August: FPGA coding and TDC Programming for beam test, with support from ATLAS interface people (RODs)

Cost Break Down So far Cost break down: FPGA: $64, USB: $30, HPTDC: Free (for beam test – 50 EUROS otherwise), clock distributor : $35, Level translator: $45, other: $100 6 layer PCB: $800, box: $100, BGA installation: $150, total: $1450

QUARTIC 8 Channel TDC Board Prototype Minutes on Skype meeting on Feb. 8, 2008: Discussion on the opto-link from TDC board to ROD: For the time being, the opto-link will be LVDS (will be optic in the final). For beam test data taking in September, HPTDC board will be configured, online monitored through USB port, two boards will be connected to the same laptop.   At the same time, event data will be sent to the ROD through LVDS ZD0 in serial format. Clock, trigger and reset are sent via the opto-link. The ZD0 serial format will be defined by the TDC board. All signals are synchronous to the main clock ZCLK, the receiver will latch the signal on the rising edge and driver will change signal on the falling edge of ZCLK. Replace LVPECL with LVDS throughout?

Conclusion HPTDC board development is at present on track, according to stated schedule.