TFP401A-Q1 AC-Timing - Block Diagram - RGB Receive-IC AC Specification

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Presentation transcript:

TFP401A-Q1 AC-Timing - Block Diagram - RGB Receive-IC AC Specification ODCK TFP401A -Q1 RGB Receive -IC - RGB Receive-IC AC Specification Setup : 2.1ns (min) for ODLK rising edge Hold : 2.6ns (min) for ODLK rising edge Control Signals QE[23:0],QO[23:0] OCK_ONV - Timing Chart Cycle/2 : 9ns ODCK 1.8ns 0.6ns Valid Valid Setup 2.1ns Hold 2.6ns Valid Setup (max) > 11.1ns requirement Our customer uses RGB Receive-IC, and it has setup of 2.1ns and hold of 2.6ns. So, Receive-IC can not use the same ODCK edge on TFP401A-Q1. They will use rising edge on RGB Receive IC. Could you tell us the maximum setup time ?