Activity on the TO ASIC project

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Presentation transcript:

Activity on the TO ASIC project Stefano D’Amico Responsible for INFN-Lecce Year 2011

Submitted designs 2 designs (submitted in the April 2010 tape-out) has been successfully tested: -A 5bits 1GHz folding interpolated ADC -A ultra fast charge sensitive amplifier (CSP) Technology: TSMC 90nm CMOS

Technology: TSMC 90nm CMOS Chip-size: 1525umx1525um Chip Microphotograph CSP Technology: TSMC 90nm CMOS Chip-size: 1525umx1525um ADC

People People Position INFN Affiliation S. D’Amico (Responsible) Ricercatore Universitario Università del Salento INFN-Lecce G. Cocciolo PhD student M. De Matteis Post Doc A. Baschirotto Prof. Associato Università di Milano-Bicocca INFN-Milano C. Arnaboldi G. Pessina Ricercatore INFN C. Gotti

Folding/ Interpolating architecture A 5bits 1GHz ADC Folding/ Interpolating architecture The folding/interpolating architecture needs only 8 comparators instead than 31 required by a full flash ADC power saving

SNDR/SNR/SFDR vs. Input frequency

ENOB vs. Input frequency

SNDR/SNR/SFDR vs. Clock frequency

Output spectrum @fin=110MHz

Output spectrum @fin=260MHz

DNL vs. Output codeword

INL vs. Output codeword

Performance summary Parameters Values Technology CMOS 90nm Resolution 5b Conversion rate 1GS/s Supply Voltage 1.2V Input range 360mV INL/DNL 0.9LSB/0.85LSB SNDR/SNR/SFDR @fin=60MHz @fin=260MHz 37.4dB/30.2dB/36.4dB 23.6dB/27.4dB/28.9dB ENOB @fin=60MHz 4.3 3.7 ERBW 260MHz Power consumption Analog section Digital section Total 5.7mW 2.4mW 8.1mW Figure of Merit 808fJ/conv-step Core area 1mm2

Conclusions This is the last year of the activity Two high frequency test designs (ADC e CSP) in TSMC 90nm has been fully characterized A good matching between simulations and measurements has been found. A couse on digital design is planned for November 2011. The course is paid by to-ASIC (but funds for missions are missing!!!!)