Combinational Circuits Using VHDL

Slides:

Advertisements

Similar presentations

Multiplexers Section 3-7 Mano & Kime. Multiplexers & Demultiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal.

Advertisements

VHDL Structural Architecture ENG241 Week #5 1. Fall 2012ENG241/Digital Design2 VHDL Design Styles Components and interconnects structural VHDL Design.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Arbitrary Waveform Discussion 5.5 Example 34.

Multiplexer as a Universal Element Discussion D2.6 Example 9.

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Top-level VHDL Designs

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Simple Sequential Circuits in VHDL. Contents Sequential circuit examples: - SR latch in dataflow style - D flip-flop in behavioral style - shift register.

Introduction to VHDL Multiplexers. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

Combinational Logic Discussion D2.5. Combinational Logic Combinational Logic inputsoutputs Outputs depend only on the current inputs.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

ECE 331 – Digital System Design

EE 367 – Logic Design Lecture #17

ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.

ECE 448: Spring 12 Lab Midterm Exam Review. Part 1: Detailed discussion of a selected midterm from Spring Part 2: Review & discussion of common.

Data Flow Modeling of Combinational Logic Simple Testbenches

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

ENG241 Digital Design Week #4 Combinational Logic Design.

VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f

ENG2410 Digital Design LAB #5 Modular Design and Hierarchy using VHDL.

Introduction to VHDL Spring EENG 2920 Digital Systems Design Introduction VHDL – VHSIC (Very high speed integrated circuit) Hardware Description.

Mixed Style RTL Modeling

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Alexander Sudnitson Tallinn University of Technology.

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends.

CS/EE 3700 : Fundamentals of Digital System Design

5-1 Logic System Design I VHDL Design Principles ECGR2181 Reading: Chapter 5.0, 5.1, 5.3 port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Lecture #17 Page 1 ECE 4110–5110 Digital System Design Lecture #17 Agenda 1.MSI Multiplexers 2.MSI Encoders Announcements Test 1 closed book, Wednesday.

Lecture #18 Page 1 ECE 4110–5110 Digital System Design Lecture #18 Agenda 1.MSI Demultiplexers 2.MSI Tri-State Buffers 3.MSI Comparators Announcements.

Combinational logic circuit

Basic Language Concepts

Describing Combinational Logic Using Processes

ENG2410 Digital Design “Combinational Logic Design”

ECE 4110–5110 Digital System Design

Part II A workshop by Dr. Junaid Ahmed Zubairi

ECE 4110–5110 Digital System Design

Dataflow Style Combinational Design with VHDL

LIBRARY IEEE; Include Libraries for standard logic data types USE IEEE.STD_LOGIC_1164.ALL; -- Entity name normally the same as file name.

IAS 0600 Digital Systems Design

LIBRARY IEEE; Include Libraries for standard logic data types USE IEEE.STD_LOGIC_1164.ALL; -- Entity name normally the same as file name.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Data Flow Modeling of Combinational Logic

VHDL (VHSIC Hardware Description Language)

VHDL Structural Architecture

Concurrent vs Sequential

ECE 331 – Digital System Design

Data Flow Description of Combinational-Circuit Building Blocks

Modeling of Circuits with a Regular Structure

Data Flow Description of Combinational-Circuit Building Blocks

Modeling of Circuits with a Regular Structure

ECE 545 Lecture 5 Simple Testbenches.

Modeling of Circuits with Regular Structure

CprE / ComS 583 Reconfigurable Computing

Sequntial-Circuit Building Blocks

4-Input Gates VHDL for Loops

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

Digital Logic with VHDL

Presentation transcript:

Combinational Circuits Using VHDL

Contents Combinational circuit examples: multiplexer using dataflow multiplexer using behavioral style decoder using structural style

Entity Definition for 4 to 1 Multiplexer -- Define all necessary libraries library IEEE; use IEEE.STD_LOGIC_VECTOR_1164.all; entity mux_4_to_1 is port (S: in STD_LOGIC_VECTOR (1 downto 0); -- select vector S(1:0) A, B, C, D: in STD_LOGIC; -- inputs Y: out STD_LOGIC); -- outputs end mux_4_to_1;

Architecture for Multiplexer Using Dataflow -- Note: S,A,B,C,D are defined in the entity definition -- and will not be repeated here. architecture mux_4_to_1_arch of mux_4_to_1 is begin -- dataflow style (no components or processes) with S select Y <= A when "00", B when "01", C when "10", D when "11", (others => 'U') when others; -- all possibilities are covered end mux_4_to_1_arch;

Architecture for Multiplexer in Behavioral Style (Wakerely, p. 410) -- Note: S,A,B,C,D are defined in the entity definition -- and will not be repeated here. architecture mux4in8p of mux_4_to_1 is begin process (S, A, B, C, D) -- execution if there is a change in S, A, B, C, or D. begin -- All RHS variables and S are in the sensitivity list. case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= (others => 'U'); -- all possibilities covered end case; end process; end mux4in8p;

Decoder 2 to 4 in Structural Style (Ι/ΙΙ) library IEEE; use IEEE.std_logic_1164.all; entity V2to4dec is port (I0, I1, EN: in STD_LOGIC; -- two input selectors Y0, Y1, Y2, Y3: out STD_LOGIC); -- four outputs end V2to4dec; architecture V2to4dec _s of V2to4dec is signal NOTI0, NOTI1: STD_LOGIC; -- internal wires. -- definition of required component (from IEEE) component inv port (I: in STD_LOGIC; O: out STD_LOGIC); end component;

Decoder 2 to 4 in Structural Style (ΙΙ/ΙΙ) component and3 port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC); end component; begin -- inside the architecture, everything is executed in parallel U1: inv port map (I0, NOTI0); -- can read inputs … U2: inv port map (I1, NOTI1); -- and output to NOT10, NOT1 U3: and3 port map (NOTI0, NOTI1, EN, Y0); -- gate to outputs … U4: and3 port map ( I0, NOTI1, EN, Y1); U5: and3 port map (NOTI0, I1, EN, Y2); U6: and3 port map ( I0, I1, EN, Y3); end Vto4dec_s;