Digital Logic & Design Dr. Waseem Ikram Lecture No. 30

Recap Up/Down Counter IC 74HC190 Up/Down Counter Counter Decoding 3-bit down synchronous down counter Up-down counter IC 74HC190 Up/Down Counter Counter Decoding IC Counter Decoding Digital Clock Divide by 60 counter

Frequency Counter (fig 3a, 3b) Counter Applications Digital Counter Divide by 60 counter timing diagram (fig 1a, 1b) Hours Counter circuit (fig 2a) Hours Counter timing diagram (fig 2b) Frequency Counter (fig 3a, 3b) Sampling intervals (fig 4) Detailed Circuit diagram (fig 5a ) Timing diagram (fig 5b)

Timing diagram of the divide by 60 minutes/seconds counter

Timing diagram of the divide by 60 counter at time interval t56 to t64

Hours Counter Circuit

Hours Counter timing diagram

Frequency Counter Circuit

Timing diagram of the Frequency Counter Circuit

Cascaded Counter circuit for obtaining accurate sampling intervals

Detailed circuit diagram of a frequency counter

Timing diagram of the frequency counter circuit

Clocked Sequential State Machine (Mealy Machine)

Clocked Sequential State Machine (Moore Machine)

State diagram of a 3-bit Up-Counter

Design of Sync. Counters Clocked Sequential circuits (fig 6a, 6b) State diagram (fig 7)