Development of the Data Handling Processor DHP Hans Krüger – University of Bonn

Participating Institutes University of Barcelona University Ramon Llull (Barcelona) University of Bonn MPI Munich, HLL H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

Module Layout DHP chip mounted on sensor module >90% data reduction 1-2 serial links per module side Data handling hybrid DHH connects multiple modules to the DAQ system GBit link H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

DCD + DHP Signal Processing H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

Signal Flow and Data Rates DCD: modified ILC design 9x16 cells, x4 output multiplexer H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

DHP Signal Processing data processing frame buffer (5-10) common mode & pedestal correction 0-suppr. triggered r/o generate DCD & Switcher control signals clock slow control H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

DHP Design Blocks slow control (I2C interface, DAC, slow ADC, command decoder for DCD/SW )  UBarcelona PLL/DLL clock management  UBonn sequencer/state-machine for DCD/SW fast control ?? UBonn, UHD cluster finding  MPI memory cells (Hamming correction, FPGA based tests)  URL memory cells (ASIC implementation)  MPI LVDS TX/RX  UBonn Gigabit Transmission (PHY, coding: 8B/10B, FEC)  URL, UBonn de-serializer + c.m./ped. correction, 0-suppr.  UBonn trigger handling  UBonn, MPI Module interconnect (flip chip & routing)  MPI Interface DHP <-> DHH and DHH <-> back-end electronic  URL H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

Technologies 130 nm good for analogue performance (i.e. clock management chip DCM), many function blocks and libraries readily available 90 nm better for digital performance and size constraints IBM and Chartered 90nm technologies fully compatible (technology alliance) Vendor (90 nm) min. block size [mm2] price [$] [€] price/mm2 [€] bump bond pitch [µm] UMC (Europractice) std. MPW 16 41.800 2.613 162 ? mini@sic 3.5 7.000 1.991 IBM (MOSIS) 100.000 62.500 3.906 200  min 4 25.000 15.625 TSMC 89.910 56.194 3.512 180 9.850 6.156 1.539 Chartered (own MPW runs) ??? H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

Milestones - preliminary PLL chip (clock generator)  design started, submission Mar 09 Data processing blocks, FPGA implementation  started (DCD test system) Two small chip submissions DHP 0.1 test chip (single DCD chip, limited functionality)  end 2009 ? DHP 0.2 test chip (single DCD chip, full functionality)  mid 2010 ?? Full chip submission DHP 1.0  end 2010 ??? H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08

Status First DHP designers meeting (Barcelona, 11th October 2008) DHP specifications (need more input: timing, DHH…) tools & technology: IBM 90nm, Cadence OpenAccess, CLIO Soft (version control) sharing of design blocks / tasks Action points define interface to DCD and Switcher (slow control, clock/sync, data format …) estimate chip size (& power) assess impact of routing constraints on the module substrate (bump bond footprint, signal & power routing) detailed planning of milestones & time-line H. Krüger, DEPFET-SuperBelle Meeting, Karlsruhe , 2.12.08