A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic Divider IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004 班級：積體所碩一 學生：林欣緯 指導教授：林志明 教授

Outline Introduction Synthesizer Architecture Synthesizer Building Blocks Experimental Results Conclusion

Introduction 1 Being intended for mobile operations, the radio transceiver has a limited power budget. The first stages of the divider that often dissipates half of the total power. The first stage of the divider cannot be implemented in conventional static CMOS logic.

Introduction 2 Source-coupled logic (SCL) allows higher operating frequency, but burns more power. The TSPC design allows to drive the dynamic latch with a single clock phase, thus avoiding the skew problem. Dynamic latches are known to be faster and more compact than static ones.

Pulse-Swallow (P-S)*N (N+1)*S Clock：(N+1)*S+(P-S)*N =N*P+S

Synthesizer block schematic

Dynamic TSPC ÷2 divider

Extended-TSPC ÷2/3 divider

Schematic of the VCO

Chip photograph The PLL core occupies only 0.55×0.9mm2 The power supplies of the VCO and the divider have been separated on chip. The digital and the analog sections have been separated by oxide trenches, in order to avoid substrate cross-talk.

Measured tuning characteristics of the VCO

Measured output spectrum of the locked PLL

PLL phase noise spectra at fout= 5.44 GHz with narrowband filter -116dBc/Hz

PLL phase noise spectra at fout= 5.44 GHz with wideband filter

Synthesizer Performance

Conclusion The adoption of dynamic dividers in CMOS PLL for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the PLL.

Reference S. Pellerano, S. Levantino, Member, IEEE, C. Samori, Member, IEEE, and A. L. Lacaita, Senior Member, IEEE , “A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider,” IEEE J. Solid State Circuits, vol. 39, NO. 2, Feb 2004.