Proof of Concept Test Board JAZiO Proof of Concept Test Board DATA (16) PAT GEN DRVRs PAT GEN RCVRs VTR (2) RING OSC 9” COMP BER M/S MASTER M/S SLAVE Test chip demonstrates JAZiO high bandwidth I/O technology 16 data bit transmissions on both edges of a pair of voltage and timing reference (VTR) signals On chip ring oscillator for clock generation Programmable data rates up to 2Gb/s per wire from master to slave Algorithmic data pattern and (233-1) PRBS generation and self test with BER measurement Demo Chip: 0.18u TSMC, Standard ESD No PLL/DLL, pre-emphasis, encoding, or deskew Package: 120 Pin TQFP, 5nH Center-8nH Corner, <$1.00 PC Board: FR4 with lowest cost, highest availability components Bit Error Rate: PRBS (233-1) >100hrs operation with no failures; equiv to >1016 I/O Power: <25mW per I/O Skew 285 pS Data Rate 1.5 Gigabits/Sec/Pin