The Design of a Low-Power High-Speed Phase Locked Loop Tiankuan Liu1, Datao Gong1, Suen Hou2, Zhihua Liang1, Chonghan Liu1, Da-Shung Su2, Ping-Kun Teng2, Annie C. Xiang1, Jingbo Ye1 1 Department of Physics, Southern Methodist University, Dallas TX 75275, U.S.A. 2 Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan liu@mail.physics.smu.edu

Outline Introduction PLL Design PLL performances Conclusion Block diagram Layout VCO design and simulation Divider design and simulation PLL performances Acquisition time Deterministic jitter Random jitter Conclusion Acknowledgments

Introduction Application background ATLAS Liquid Argon Calorimeter Optical Link Upgrade Present Upgrade Data rate per front-end board (FEB) (Gbps) 1.6 100 Power consumption per Gbps (mW) 1188 90 Silicon-on-Sapphire (SoS) CMOS technology High speed, low power, high quality inductors, no latch-up The radiation tolerance of a commercial 0.25 µm SoS CMOS technology has been evaluated in the previous study Design Goals: Operation frequency: 4 ~ 5 GHz for data rate 8 ~ 10 Gbps Random jitter < 1 ps (RMS) Power consumption < 100 mW

PLL Design: Block Diagram Phase frequency detector Test points LC-tank based voltage controlled oscillator (VCO) Divider (divide by 16) LVDS Receiver is the input interface CML driver is used to drive 50 Ω coaxial cables charge pump with programmable current (20, 40, 60, 80 µA) 2nd order passive Low pass filter with programmable bandwidth

PLL Design: Shared Blocks The LVDS receiver, the phase frequency detector (PFD), the charge pump, the pass filter, the CMOS divider, and the CML driver are shared with the 5 Gbps 16:1 serializer. For details of these design blocks please see the poster “A 16:1 serializer for data transmission at 5 Gbps” presented by Dr. Datao Gong at TWEPP, Paris France, September, 2009. The bandwidth of the low pass filter and the current of charge pump are programmable to suit different applications. The loop bandwidth and the phase margin are calculated in the following table. Configuration C0C1C2 001 010 100 BW (MHz) phase margin (deg) Charge pump gain (µA) 20 0.42 46.33 0.84 46.34 1.68 40 0.72 56.29 1.44 56.30 2.88 56.31 60 1.02 59.50 2.04 4.08 59.53 80 1.31 59.99 2.63 5.25 60.04

PLL Design: Layout Area 1.4 mm x 1.7 mm

PLL Design: VCO Comparison of two common type VCOs VCO Type LC-tank based VCO Ring oscillator-based VCO Power Consumption Low High Frequency Phase noise/jitter performance Good Bad Radiation sensitivity Small Large Tuning range Narrow Wide Chip area

PLL Design: VCO Schematic Cross-coupled transistors provides negative resistance, compensating the energy loss in the LC tank Decoupling capacitors are used to improve the noise performance On-chip spiral inductors with a peak frequency of 5.1 GHz. The Q factor is simulated to be 21.2 at 5 GHz. A NMOS or PMOS transistor with its source and drain tied together serves a varactor with monotonic C-V curve and large tuning range (Cmax/Cmin > 2). Start-up circuit Reference current source

PLL Design: VCO Simulation The tuning range is 3.79 – 5.01 GHz at the typical corner and room temperature and varies less than 8% in all corners and temperature range.

PLL Design: Dividers The divider consists of a CML divider (divide by 2), a CML to CMOS converter, and a CMOS divider (divide by 8) The dividers can work up to 5.1 GHz at all corners from -40 °C to 85 °C

PLL Design: CML Divider

PLL Design: CML to CMOS Converter

PLL Performances: Acquisition Time The PLL tracks the input frequency and phase after 9 µs

PLL Performances: Deterministic Jitter The deterministic jitter after tracking (9 µs) is less than 2 ps (peak-peak)

PLL Performances: Random Jitter The random jitter due to the VCO’s phase noise, the dominant noise source, is less than 1 ps (RMS) from 10 kHz to 100 MHz The phase noise of the VCO in the worst case

Conclusion: Simulated Results of the PLL Tuning range (GHz) 3.78 – 5.01 power consumption (core PLL mW) 104 Area (including pads and decoupling caps, mm2) 1.4 x 1.7 Random Jitter from VCO (RMS, ps) < 1 Deterministic jitter after locking (peak-peak, ps) 2 Acquisition time (μs) 9

Conclusion: Status and Plan Fabrication: submitted on August 3, 2009; Chip delivery: November 28, 2009 Test: in lab test: December 15, 2009; Radiation test: February - March, 2010 Plan: apply this LC-based PLL and design a multi-channel 16:1 serializer with each channel working around 10 Gbps in 2011

Acknowledgments Grant: US-ATLAS R&D program for the upgrade of the LHC and the US Department of Energy grant DE-FG02-04ER41299. Peter Clarke, Jay Clementson, Yi Kang, Francis M. Rotella, John Sung, and Gary Wu from Peregrine Semiconductor Corporation for technical assistance. Justin Ross at Southern Methodist University for setting up and maintaining the software environment. Jasoslav Ban, Mauro Citterio, Christine Hu, Sachin Junnarkar, Valentino Liberali, Paulo Rodrigues Simoes Moreira, Mitch Newcomer, Quan Sun, Fukun Tang, and Carla Vacchi for technical assistance and reviewing of this design.