Calibration On pixel calibration capacitor; 20fF For 20fC signal we need 1V amplitude and edge from 2 to 3ns range Internal circuit; switching current on resistance, for 1V signal difficult, work reasonable up to 500mV (calibration up to 10fC  is that sufficient?) power about 500uA in this case (higher resistor will give too high time constant and edge will be > than 3ns) External circuit; Distance between chips in 10cm range, that means that for 1ns edges signal(GHz range) the load seen by pulse generator will be complex. With 50 Ohm output impedance we should limit the total capacitance down to about 5-6pF. So for safe operation we should use 4 calibration lines per hybrid. With special ESD protection arrangement we can have pad with 1pF parasitic capacitance (standard is 3pF). Limit for ESD protection is around 2V so the maximum calibration signal will be 40fC (can go up to 60fC if neccessary but this should be done only for prototype chips). It is difficult and complicated to make the internal calibration circuit which can be forced outside the chip.