TDC at OMEGA I will talk about SPACIROC asic SPACIROC stands for Spatial…….

Time to Amplitude Convertor Analog ramp (25 ns) followed by a 10-bit wilkinson ADC integrated in several ROC chips, 25ps bin, 1mW per channel, 0,35um AMS SiGe SKIROC SPIROC CATIROC PETIROC (OMEGA/WeeRoc) FE: Broad Band SiGe fast amplifier, Fast SiGe discriminator 1 GHz overall bandwidth, gain = 25 SKIROC2-CMS TDC (TAC) for ToT and ToA, accuracy 50ps More detailed measuremenents with Petiroc (AMS SiGe 0.35µm): Can be used either in full digital mode using the internal TAC or in analogue mode using the 32 trigger outputs and the multiplexed charge output. The analogue mode enables the use of external TDC Measurements on testbench in both modes, by IPNL in analog mode (external TDC), by Baptiste Joly (Clermont) in digital mode Bénodet 17 May 2017

PETIROC2A: TAC Testbench measurement Use of a 40 MHz and 160 MHz clock, seen on the TDC (residuals) => affects the time resolution rms of the histogram of the residuals: 2.6 ADC Unit Time resolution: 2.6x37ps (step)= 96 ps rms Bénodet 17 May 2017

Testbench measurements (2) Correction factors @Baptiste Joly to correct for the clock coupling Before correction: Amplitude=5 mV sdev=150 ps Amplitude=10 mV sdev=120 ps Amplitude=20 mV, sdev=100ps After correction: Ampl=5 mV, delay=2.5 ns => sdev=80 ps After correction: Ampl=10 mV, delay=2.5 ns => sdev=60 ps After correction: Ampl=20 mV, delay=2.5 ns => sdev=54 ps Bénodet 17 May 2017

Electrical tests for RPC: analog mode Measurement of both strip’s ends via 2 channels of the same PETIROC ASIC . Corresponding discriminator outputs of ASIC is sent to a TDC on FPGA ( Altera Cyclone II) σt ≃ 20-30 ps PETIROC Off-detector strip path Mezzanine with FPGA Currently, 19 channels are implemented on the FPGA  measurement of 8 strip, with two channels per strip. Bénodet 17 May 2017

Measurement at CERN in FAST framework CTR with LSO + SiPM + NINO and PETIROC and 22Na CTR = 110 ps FWHM, similar to NINO alone SPTR = 67 ps rms = 180 ps FWHM (x2 digital mode) © S. Gundacker (CERN) Bénodet 17 May 2017

CdLT HGCAL electronics Lyon 16 mar 2017 Time of arrival (ToA) TOA measured with internal TDC and corrected for time walk Constant term = 50 ps OK, noise term = 10ns/Q(fC) © J. Borg ICL CdLT HGCAL electronics Lyon 16 mar 2017

HGROCv1 - Design Review - April 26, 2017 DLL-based TDC Based on a global 32 DLL at 640 MHz, 50ps bin 13 bits (400ns to 50ps accuracy) + 1 Extrabit Lock time: ~ 1 μs Mismatch: 5ps rms on the bin ~ 3,7 mW/channels with 32 channels (dominated by buffers) HGROCv1 - Design Review - April 26, 2017

CONCLUSIONS TAC: Low power: ~ 1mW per channel Large dead time Coupling of the 40 MHz and 160 Mhz clocks 160 MHZ clock can be avoided Coupling through the substrate using AMS SiGe 0.35 µm: could be avoided with 130 nm technlogy Bénodet 17 May 2017

BACKUP Bénodet 17 May 2017

PETIROC2 DESCRIPTION AMS 0,35µm SiGe Front-end Time of Flight read-out chip with embedded TDC (25 ps bin) and ADC Dynamic range: 160 fC up to 400 pC 32 channels (negative input) 32 trigger outputs NOR32_chrage NOR32 time Charge measurement over 10 bits Time measurement over 10 bits One multiplexed charge output Common trigger threshold adjustment and 6bit-dac/channel for individual adjustment Variable shaping time of the charge shaper 32 8bit-input dac for SiPM HV adjustment Power consumption 6 mW/ch Front-end Broad Band SiGe fast amplifier Fast SiGe discriminator 1 GHz overall bandwidth, gain = 25 AMS 0,35µm SiGe Bénodet 17 May 2017

Delay Cell: Mismatch et PVT simulations HGROCv1 - Design Review - April 26, 2017