Production of 3D silicon pixel sensors at FBK for the ATLAS IBL Alvise Bagolinia, Maurizio Boscardin a, Gian-Franco Dalla Bettab, Gabriele Giacominia, Francesca Mattedia, Marco Povolib, Nicola Zorzia a Fondazione Bruno Kessler (FBK-CMM) Italy b INFN and University of Trento, Italy

3D silicon pixel sensor production The layout has been developed in the in the framework of the ATLAS 3D Sensor Collaboration FE-I4 (8x) FE-I3 (9x) CMS (3x) test structures 3D_DDTC with passing-through columns technology was used for the first production oriented to the ATLAS insertable B-Layer

Layout details of a FE_I4 sensor Ohmic Side Junction side 50 µm 125 µm FE-I4 sensor  80 x 336 pixels dead area of 200 mm

3D-DTC with passing through columns n+ col. Column depth equal to the wafer thickness, etched from both sides Full double side process Surface isolation with p-spray on both sides No support wafer Columns (~12 µm diam.) are “empty”, doped by thermal diffusion and passivated by SiO2 Edge protection in order to improve the mechanical yield p-sub t p-spray p+ col. edge protection

Main technological aspects Optimization of DRIE recipe for holes with higher aspect ratio in order to improve the uniformity of the etch rate throughout the process. Optimization of edge protection in order to increase the mechanical yield after DRIE etching reduce the wafer bowing and consequently the leakage current

Optimize DRIE recipe for holes with higher aspect ratio Etch stop for DRIE etching

Optimize edge protection Mechanical fragility of wafers manly due to a cracks on the wafer edge caused by D-RIE etch step: Need a special edge protection during DRIE etching (electrostatic clamping) to prevent the creation of cracks that could cause the breakage during the processing. Need a special care during processing Mechanical yield with the optimized edge protection:   initial wafers broken wafers mechanical yield (%) 3D ATLAS 10 25 5 80% 3D ATLAS 11 3 88% 3D ATLAS 12 23 6 74% 3D ATLAS 13 20 8 60%

Optimize edge protection: wafer bowing Edge protection effects on the wafer bowing. A high bowing induces High leakage current Misalignment among columns Bonding problem Old edge protection  wafers warp up to 120 µm Optimized edge protection  wafers warp < 30 µm 3D_ATLAS10

Wafer bowing: leakage current The wafer bowing strongly influences the leakage current. With the optimized edge protection it is reduced of one order of magnitude. Leakage current on planar test diodes (4mm2) Old edge protection Optimized edge protection

Wafer bowing: Column alignment left side center right side old edge protection misalignment of a several μm optimized edge protection layer Misalignment < 5μm

Temporary metal for electrical characterization The temporary metal shorts 336 pixels together in a strip Allows to perform electrical tests on the FE-I4 pixel sensors before bump-bonding The IV characteristics of 80 strips form a FE-I4 pixel sensor 336 pixels ( 2 electrodes per pixel) 80 strip

Temporary Metal: IV characteristics The IV characteristics of 80 strips of two sensors The IV characteristics of FE-I4 pixel sensor as a sum of 80 IV strips curves

VBD and Ileak of the FE-I4 strips Good uniformity from batch to batch related to the 80 strips of each detector

Yield on Selected Wafers (%) Numbers of production 4 production batches Batch Tested Wafers Selected Wafers Total Sensors Number of Good Sensors Yield on Selected Wafers (%) 3D ATLAS 10 20 12 96 58 60% 3D ATLAS 11 11 4 32 14 44% 3D ATLAS 12 16 13 104 63 61% 3D ATLAS 13 15 47% Selected wafers  at least 3 FE-I4 sensors qualified Selection criteria before bump-bonding: Vdepl ≤ 15V and Vop ≥ Vdepl +10V I (Vop) < 2mA per tile Vbd > 25V [I (Vop) / I(Vop – 5V)] < 2

Problem Investigation on 3D_Atlas11 Litho n+ on junction side Problem with resist adhesion Low final yield

Conclusion Outlook Upgrade to 6 inch FBK has developed and optimized the technology used for the production of Si-3D pixel sensors for the ATLAS IBL with a relatively good yield. Outlook advantages Production capability = double the wafers area DRIE upgrade with a thin ceramic edge protection = increasing of the mechanical yield Upgrade to 6 inch disadvantage We have to learn how to process a thin wafers