Arithmetic and Logic Units Department of Communication Engineering, NCTU

4.1 Serial Adder with Accumulator Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU We design a control circuit for a serial adder with an accumulator Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Operation Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU State graph for serial adder control Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU 4.2 A Parallel Multiplier Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU A multiplier for binary positive number Save the product in a register Shift the product to the right each time Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Datapath of the multiplier Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Operation for a simple example Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU State graph for a straightforward implementation Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU An alternative approach Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Operation using a counter Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU 4.3 A binary Divider Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU A parallel divider for positive numbers A circuit to divide an 8-bit dividend by a 4-bit divisor to obtain a 5-bit quotient Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Block diagram Store the dividend in a register Shift the dividend to the left each time An extra bit is required on the left end of the dividend register Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU The operation for an example Load initial data Subtraction cannot be carried out without a negative result Thus, shift the dividend to the left before we subtract Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU The quotient digit of 1 is stored in the unused position of the dividend register Shift the dividend one place to the left Shift once again The first quotient digit Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Subtraction is carried out, and the 3rd quotient digit of 1 is stored in the unused position of the dividend register A final shift is carried out, and the 4th quotient bit is set to zero What if the quotient is too large > 4 bits If the initial left five bits  the divisor overflow Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Datapath Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU The state graph If X8 X7 X6 X5 X4  Y3 Y2 Y1Y0  C =1  Sh and Sub and the quotient bit is 1 Otherwise  Sh and the quotient bit is 0 Department of Communication Engineering, NCTU

Department of Communication Engineering, NCTU Implementation with the one-hot assignment Department of Communication Engineering, NCTU