Dr. Clincy Professor of CS

Slides:

Advertisements

Similar presentations

Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.

Advertisements

컴퓨터구조론 교수 채수환. 교재 Computer Systems Organization & Architecture John D. Carpinelli, 2001, Addison Wesley.

Digital Design: Combinational Logic Blocks

Give qualifications of instructors: DAP

Combinational Logic with Verilog Materials taken from: Digital Design and Computer Architecture by David and Sarah Harris & The Essentials of Computer.

1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.

©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.

Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals.

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Timing Sequential Logic Flip Flops Registers Memory State Machines.

Multiplexers, Decoders, and Programmable Logic Devices

ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.

Programmable Array Logic (PAL) Fixed OR array programmable AND array Fixed OR array programmable AND array Easy to program Easy to program Poor flexibility.

طراحی مدارهای منطقی نیمسال دوم دانشگاه آزاد اسلامی واحد پرند.

Part 2: DESIGN CIRCUIT. LOGIC CIRCUIT DESIGN x y z F F = x + y’z x y z F Truth Table Boolean Function.

Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 13 – Programmable.

Figure to-1 Multiplexer and Switch Analog

Combinational Circuits Chapter 3 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003.

Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Logic Circuits I.

Digital Components and Combinational Circuits Sachin Kharady.

1 Lecture #7 EGR 277 – Digital Logic Reading Assignment: Chapter 4 in Digital Design, 3 rd Edition by Mano Chapter 4 – Combinational Logic Circuits A)

Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP

Lecture 9 Topics: –Combinational circuits Basic concepts Examples of typical combinational circuits –Half-adder –Full-adder –Ripple-Carry adder –Decoder.

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

Digital Logic Structures: Chapter 3 COMP 2610 Dr. James Money COMP

CEC 220 Digital Circuit Design Programmable Logic Devices

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

COMBINATIONAL AND SEQUENTIAL CIRCUITS Guided By: Prof. P. B. Swadas Prepared By: BIRLA VISHVAKARMA MAHAVDYALAYA.

Chapter 3 Boolean Algebra and Digital Logic T103: Computer architecture, logic and information processing.

Chapter 36 Combinational Logic Circuits. Objectives After completing this chapter, you will be able to: –Describe the functions of encoders, decoders,

Programmable Logic Devices

Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.

Programmable Logic Devices

Chapter- 9 Programmable Logic Devices DHADUK ANKITA ENRL NO Noble Engineering College- Junagadh.

CENG 241 Digital Design 1 Lecture 13

This chapter in the book includes: Objectives Study Guide

ETE Digital Electronics

Digital Design Lecture 14

Sequential Logic Design

CS Chapter 3 (3A and ) Part 6 of 8

This chapter in the book includes: Objectives Study Guide

Programmable Logic Devices

ECE 2110: Introduction to Digital Systems

Logic and Computer Design Fundamentals

Lecture 9 Logistics Last lecture Today HW3 due Wednesday

CS Chapter 3 (3A and ) – Part 4 of 5

This chapter in the book includes: Objectives Study Guide

Summary Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out.

Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

Dr. Clincy Professor of CS

FIGURE 7.1 Conventional and array logic diagrams for OR gate

حافظه و منطق قابل برنامه ریزی

CSCE 211: Digital Logic Design

CSCE 211: Digital Logic Design

FIGURE 4.1 Block diagram of combinational circuit

حافظه و منطق قابل برنامه ریزی

Programmable Logic Devices

Programmable Configurations

Lecture 10 Logistics Last lecture Today

Number Systems and Circuits for Addition

Dr. Clincy Professor of CS

Dr. Clincy Professor of CS

CSCE 211: Digital Logic Design

CSCE 211: Digital Logic Design

Combinational Circuits

Logic Circuits I Lecture 3.

Electronics for Physicists

Digital System Design Combinational Logic

PROGRAMMABLE LOGIC DEVICES (PLD) UNIT-IV

FIGURE 5-1 MOS Transistor, Symbols, and Switch Models

Presentation transcript:

Dr. Clincy Professor of CS CS 6021 - Chapter 3 Dr. Clincy Professor of CS Dr. Clincy Lecture Slide 1 1

Half Adder - Combinational Circuits Combinational logic circuits give us many useful devices. One of the simplest is the half adder, which finds the sum of two bits. We can gain some insight as to the construction of a half adder by looking at its truth table, shown at the right. Dr. Clincy Lecture

Full Adder - Combinational Circuits We can change our half adder into to a full adder by including gates for processing the carry bit. The truth table for a full adder is shown at the right. Dr. Clincy Lecture

Adders - Combinational Circuits Just as we combined half adders to make a full adder, full adders can be connected in series. The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carry adder. Today’s systems employ more efficient adders. Dr. Clincy Lecture

Decoder - Combinational Circuits Among other things, they are useful in selecting a memory location according to a binary value placed on the address lines of a memory bus. This is what a 2-to-4 decoder looks like on the inside. If x = 0 and y = 1, which output line is enabled? Output - Decoded message Input - Encoded message Dr. Clincy Lecture

Decoder – another example Dr. Clincy Lecture

Multiplexer - Combinational Circuits A multiplexer does just the opposite of a decoder. It selects a single output from several inputs. This is what a 4-to-1 multiplexer looks like on the inside. Depending the “select input” combination, 1 of 4 data inputs is chosen for output If S0 = 1 and S1 = 0, which input is transferred to the output? Dr. Clincy Lecture

Multiplexer - Combinational Circuits Can also use multiplexers to implement logic functions Given this truth table, group X1,X2 being 00, 01, 10 and 11 – notice what happens with X3 3-input truth table can be done with a 4-input mux 4-input truth table can be done with a 8-input mux 5-input truth table can be done with a 16-input mux Etc.. Also explain how the Mux is used to implement data comm’s FDM and TDM Dr. Clincy Lecture

10.2.2 - Programmable Logic Devices (PLD) All possible combinations of inputs ANDed   ••• All possible combinations of ANDed inputs ORed   Re-explain Sums of Products and relationship to PLDs Dr. Clincy Lecture

10.2.2 - Programmable Logic Array (PLA) Ability to program a PLD, is called a PLA Dr. Clincy Lecture

10.2.2 - Programmable Array Logic (PAL) For a PLA, both the AND array and OR array are programmable For a PAL, the AND array is programmable and the OR array is fixed Dr. Clincy Lecture

10.2.2 - Complex Programmable Logic Devices (CPLDs) CPLDs are comprised of 2 or more PALs Dr. Clincy Lecture

10.2.2 - Field Programmable Gate Arrays (FPGAs) PAL chips are somewhat limited in size due to the fact they have output pins for each sum-of-product circuit FPGA overcome this size limitation by using a general interconnection. General interconnection PAL Dr. Clincy Lecture