Output Prediction Logic (OPL)

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Presentation transcript:

Output Prediction Logic (OPL) ECE632 Lukasz Szafaryn and Blake Sheridan 04 Dec 07

Outline Project Goals New Logic Family How OPL Works 16-bit CLA Adder with OPL Effect of Variation Summary Questions ?

Project Goals Familiarize ourselves with OPL Implement a high-speed adder using OPL Create methodologies for designing OPL circuits Test the effects of process variation on the adder

New Logic Family? Logic Design Static Dynamic Output Prediction

How OPL works 1) Precharge: 1 1 1 ? 1 2) Evaluate: 1 X 1 1 X

Clock Synchronization Output evaluation in each stage is triggered by clocks

16-bit CLA Adder

4-bit CLA Adder Unit w/o OPL w OPL

OPL Adder Performance Adder architecture is very parallelized At each clock stage we saved about 0.5ns The total time for addition is input dependent We tested several combinations of inputs including the two which we deemed to be the best case and worst case: 0000 0000 0000 0000 + 0000 0000 0000 0001 with the speedup of 1.2 0000 0000 0000 0001 + 1111 1111 1111 1111 with the speedup of 1.125

Effects of Variance Variance primarily affects the pull-up and pull-down of outputs shortly after CLK goes high (eval): A smaller NMOS causes an output’s fall to zero to take too long, resulting in a loss of speed A smaller PMOS results in a slower pull up, though the effect is less pronounced

Effects of Variance no variance stronger pmos stronger nmos

Summary OPL is an interesting concept and an addition to traditional static logic OPL can be applied to digital circuits to improve their speeds Application of OPL to complex circuits is challenging Component variation has a small effect on OPL performance – non-ideal transistors will slow down the circuit

References [1] McMurchie, L., Kio, S., Yee, G., Thorp, T., & Sechen, C. (2000). Output Prediction Logic: a High-Performance CMOS Design Technique. Seattle: University of Washington. [2] Sun, S., McMurchie, L., & Sechen, C. (2001). A High- Performance 64-bit Adder Implemented in Output Prediction Logic. Seattle: University of Washington. [3] McNish, R. , & Nalam, S. (2003). A High Performance Low Power 64 bit OPL-Static Adder. Seattle: University of Washington. [4] Han, Y., McMurchie, L., & Sechen, C. (2005). A High Performance CMOS Programmable Logic Core. Seattle: University of Washington.