Front-end digital Status Acquisition tools to test Analog part. Tools to test A3PE FPGA (SSO & SSI) Next steps Radiation tests Prototype FEB 8 Channels Caceres Thierry Duarte Olivier LHCb Calorimeter upgrade meeting

Reminder : Typical acquisition sequence Write Acq Register (PC) Beginning L0 sequence 1 2 3 Time Trigger Generator 1 2 3 1 2 3 Data readout by USB Write Data Ctrl 25 ns to 65,5µs Discret Time Beginning latency delay Recording data in RAM (512 points) End of latency delay FIFO full PC write start sequence bit of Acquisition (Acq) Register. Beginning of L0 sequence. Each trigger pulse involve pulse shape. At the end of the latency delay recording 512 points of data (Max). At the end of the record the system write one “end of acquisition”bit in the Acq_Register . The PC scrutinize the Acq_Register, when the “end of acquisition” is high the PC download data with the USB interface. LHCb Calorimeter upgrade meeting June 15th 2012

Tools to test Analog part : “Acquisition system” ADC emulation SPY data FIFO pattern Generate digital signals Check FPGA computations SPY FIFO storage of processing results ANALOG PULSE FIFO generate trigger of analog pulses 96 PATTERN_FIFO 96 96 8 USB_data Buffer_FIFOs (12x8) USB wr WR RD (96 x 512) {Add 0x1C} 96 1 Wr : USB Rd : USB or 40 Mhz 96 SPY_FIFO 1 96 96 8 (x8) 96 96 USB data WR RD 12 bit ADC data from Analog Mezzanine (96 x 512) 8 x 12bits setup_ register[9] {Add 0x06} USB_data setup_ register[8] Wr : USB or 40 Mhz Rd : USB 8 8 8 8 TRIGGER_FIFO Analog Pulse ( 1 per ADC Channels) WR RD 8 USB_data 1 ClkUSB (8 x 512) {Add 0x1F} From MUX Clk_USB / Clk_1 MUX Clk_USB / Clk_40Mhz Wr : USB Rd : USB or 40 Mhz Clk 40 Mhz A3PE setup_register[9] Trigger for Analog LHCb Calorimeter upgrade meeting June 15th 2012

Tools to test A3PE FPGA (SSO & SSI) Idea : RAM pattern to test the A3PE IOs functioning by exchanging data between the 2 FPGA (SSO and SSI) USB Rd / Wr the RAM (To_AX and From_AX). Buffer_FIFOs 32 1 ClkUSB To_AX_RAM 32 MUX Clk_USB / Clk_1 Sequence: To_AX _RAM Rd/Wr by USB Start commande Loop on to AX_RAM until stop command Programmable latency to capture data from To_AX_RAM to FROM_AX_RAM CLK_1 Wr Rd (32 x 512) From Delay Chip {Add 0x1D} Wr : USB Rd : USB or Clk_1 setup_register[11] 8 USB_data Ctrl. Wr / Rd pattern 32 32 32 32 32 32 32 RegUSB 32 32 BUSMSB AXTOA3PE setup_register[10] _q _q1 32 32 Start / Stop and latency (implemented !) 1 USB_data 8 32 From_AX_RAM 32 32 Rd Wr (32 x 512) 32 {Add 0x1E} 32 32 32 Wr : USB or Clk_1 Rd : USB setup_register[11] BUSLSB AXTOA3PE USB_data 8 32 A3PE _q3 _q2 AX500 LHCb Calorimeter upgrade meeting June 15th 2012

Start Stop Latency sequence Buffer_FIFOs 32 Start Stop Latency sequence 1 ClkUSB To_AX_RAM 32 CLK_1 Wr Rd (32 x 512) From Delay Chip {Add 0x1D} Wr : USB Rd : USB or Clk_1 setup_register[11] 8 USB_data Ctrl. Wr / Rd pattern 32 32 32 32 32 32 32 RegUSB 32 32 1 BUSMSB AXTOA3PE _q _q1 setup_register[10] 32 32 1 USB_data 8 32 From_AX_RAM 32 32 Rd Wr (32 x 512) 32 {Add 0x1E} 32 32 32 Wr : USB or Clk_1 Rd : USB setup_register[11] BUSLSB AXTOA3PE USB_data 8 32 A3PE _q3 _q2 AX500 START / STOP / LATENCY SEQUENCE Status: Firmware implemented Cycle Ok Rd / Wr by USB Ok Internal loop In progress External loop (AX FPGA) In progress 3 boards in used START SEQ LATENCY Tunable latency Rd To AX RAM Loop Wr From AX RAM 512 words writed STOP SEQ LHCb Calorimeter upgrade meeting June 15th 2012

Prototype FEB 8 Channels Some idea of architecture …. Analog FE part (2 Ch) Analog FE part (2 Ch) 24 24 Actel FPGA Analog FE part (2 Ch) 24 One differential pair A3PE1500 (BGA480) Analog FE part (2 Ch) 24 SLVDS level ! Compatibility ? Adaptation by specific ASIC ? ASICs or discret solution 2 channels GBT 8x5x2 e-port Demux e-port GBT link Framer SerDes 8 ports @ 320 Mbps 16 ports @ 160 Mbps 32 ports @ 80 Mbps System Clock mux Used in one-way ! e-port Prototype FEB pending questions  Mezzanine board with GBT  SLVDS  E link slow control from Ctrl Board through backplane e-port Clk [0.7] User Buses and I/O signals for Control & Monitoring (I2C, JTAG, SPI, ….) From Control Board through Backplane GBT-SCA Slow Control e-link 1 port @ 80 Mbps LHCb Calorimeter upgrade meeting June 15th 2012

LHCb Calorimeter upgrade meeting Conclusion Digital electronic is ok, several adjustment have been done . Last adjustment of the tools to test A3PE FPGA (SSO & SSI). Radiation tests of components for analog and digital part . Start thinking about the prototype FEB, we considered a 8 channels prototype FEB for the beginning of 2013 with ( mezzanine ?) GBT (availability of the first GBT samples) ? LHCb Calorimeter upgrade meeting June 15th 2012

LHCb Calorimeter upgrade meeting SPARE LHCb Calorimeter upgrade meeting June 15th 2012

External clock reference FE Module E – Port Phase - Shifter CLK Reference/PLL FE Module E – Port E – Port E – Port DEC/DSCR CDR 80, 160 and 320 Mb/s ports Phase – Aligners + Ser/Des for E – Ports CLK Manager SCR/ENC SER E – Port FE Module E – Port E – Port One 80 Mb/s port Control Logic Configuration GBT – SCA JTAG I2C Slave I2C Master E – Port I2C (light) JTAG Port I2C Port Ken Wyllie, CERN LHCb electronics, 14th June 2012

Physical Layer (electrical) Kostas Kloukinas’s slide SLVS (Scalable Low Voltage Standard) JEDEC standard: JESD8-13 Differential voltage based signaling protocol. Voltage levels compatible with deep submicron processes. Typical link length runs of 30cm over PCB at 1Gbps. Low Power, Low EMI Application in data links for Flat Panel displays in mobile devices. Mobile Pixel Link, MPL-2 (National semi.) LVDS 400mV SLVS specifications brief 2 mA Differential max Line impedance: 100 Ohm Signal: +- 200 mV Common mode ref voltage: 0.2V 1.2V SLVS 200mV 0.2V LHCb Calorimeter upgrade meeting June 15th 2012

LHCb Calorimeter upgrade meeting Clock tree LHCb Calorimeter upgrade meeting June 15th 2012