Modeling Rp B R1 CL A R2 Cint

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Presentation transcript:

Modeling Rp B R1 CL A R2 Cint Scheme (models for transistor, interconnections, contacts, etc.) Layout (“Real” Circuit) Behavior may be verified by Simulation !! Microelectronic Circuits - Fifth Edition Sedra/Smith

Revisiting IDS-VDS –VGS Equations From Rabaey 2003

Revisiting IDS-VDS –VGS Equations Design Parameters From Rabaey 2003

Technology Parameters Revisiting IDS-VDS –VGS Equations Technology Parameters From Rabaey 2003

SPICE MOS-Transistor Models Transistor technology models used in detailed circuit simulation Models are classified according to levels Level 1- simplified physical model for large transistors Level 2- physical model including small transistor effects Level 3- first model with empirical parameters Level 53- used in lab; for deep submicron technology Microelectronic Circuits - Fifth Edition Sedra/Smith 5

SPICE MOS-Transistor Models Transistor technology models used in detailed circuit simulation Models are classified according to levels Level 1- simplified physical model for large transistors Level 2- physical model including small transistor effects Level 3- first model with empirical parameters Level 53- used in lab; for deep submicron technology What is the relationship between simulation (model) accuracy and design flow efficiency? Microelectronic Circuits - Fifth Edition Sedra/Smith

Spice Parameters – Level 1 Microelectronic Circuits - Fifth Edition Sedra/Smith

5 and 0,5 mm Techs. Example Microelectronic Circuits - Fifth Edition Sedra/Smith

Transistor Capacitance Parameters ? Microelectronic Circuits - Fifth Edition Sedra/Smith

Gate Capacitance Model Polysilicon gate Gate oxide t ox n + L n + Source Drain Cross section W n + n + L Top view Microelectronic Circuits - Fifth Edition Sedra/Smith

N-P Junction Capacitance

Bottom Diffusion (Junction) Capacitance Model Source W (channel width) Bottom AS: Area of source Channel Ls (Source or Drain Length) Substrate N A Microelectronic Circuits - Fifth Edition Sedra/Smith

Side-wall Diffusion (Junction) Capacitance Model (channel width) Side wall Source Side wall Side wall PS: Perimeter of source Channel Ls (Source or Drain Length) Substrate N A Microelectronic Circuits - Fifth Edition Sedra/Smith

Side-wall Diffusion (Junction) Capacitance Model Computation of Cdb (for drain) is equivalent trading AS and PS for AD and PD W (channel width) Side wall Source Side wall Side wall PS: Perimeter of source Channel Ls (Source or Drain Length) Substrate N A Microelectronic Circuits - Fifth Edition Sedra/Smith 14

Overlap Capacitance Models Gate oxide t ox Polysilicon gate n + Leff n + Cross section Source Drain W L Leff + L n d d n + L L b Gate-bulk Top view overlap Microelectronic Circuits - Fifth Edition Sedra/Smith 15

Overlap Capacitance Models Gate oxide t ox L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain W b Leff n + Leff n + Cross section Ld is included in CXXO parameters Leff= L-2.Ld (must be used in current equations if Ld is given) Microelectronic Circuits - Fifth Edition Sedra/Smith

Revisiting Gate Capacitance Model Polysilicon gate Top view Gate-bulk overlap Source n + Drain W b Leff Polysilicon gate Source Drain W n + n + L Top view Leff Microelectronic Circuits - Fifth Edition Sedra/Smith