EE 5340 Semiconductor Device Theory Lecture 25 – Spring 2011

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Presentation transcript:

EE 5340 Semiconductor Device Theory Lecture 25 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

Ideal 2-terminal MOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 y L silicon substrate tsub Vsub x ©rlc L25-21Apr2011

MOS surface states** p- substr = n-channel ©rlc L25-21Apr2011

MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|fp| qfp xd,max ©rlc L25-21Apr2011

Equivalent circuit for accumulation Accum depth analogous to the accum Debye length = LD,acc = [eVt/(qps)]1/2 Accum cap, C’acc = eSi/LD,acc Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’acc ©rlc L25-21Apr2011

Equivalent circuit for Flat-Band Surface effect analogous to the extr Debye length = LD,extr = [eVt/(qNa)]1/2 Debye cap, C’D,extr = eSi/LD,extr Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’D,extr ©rlc L25-21Apr2011

Equivalent circuit for depletion Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2 Depl cap, C’depl = eSi/xdepl Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’depl ©rlc L25-21Apr2011

Equivalent circuit above OSI Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 Depl cap, C’d,min = eSi/xd,max Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’d,min ©rlc L25-21Apr2011

Differential charges for low and high freq From Fig 10.27* ©rlc L25-21Apr2011

Ideal low-freq C-V relationship Fig 10.25* ©rlc L25-21Apr2011

Comparison of low and high freq C-V Fig 10.28* ©rlc L25-21Apr2011

Effect of Q’ss on the C-V relationship Fig 10.29* ©rlc L25-21Apr2011

Flat band condition (approx. scale) SiO2 p-Si q(fm-cox)= 3.15 eV q(cox-cSi)=3.1eV Ec,Ox qffp= 3.95eV EFm Ec Eg,ox~8eV EFi EFp Ev Ev ©rlc L25-21Apr2011

Flat-band parameters for n-channel (p-subst) ©rlc L25-21Apr2011

Flat-band parameters for p-channel (n-subst) ©rlc L25-21Apr2011

Typical fms values Fig 10.15* fms (V) NB (cm-3) ©rlc L25-21Apr2011

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev ©rlc L25-21Apr2011

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 ©rlc L25-21Apr2011

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh ©rlc L25-21Apr2011

MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|fp| qfp xd,max ©rlc L25-21Apr2011

Computing the D.R. W and Q at O.S.I. Ex Emax x ©rlc L25-21Apr2011

Calculation of the threshold cond, VT ©rlc L25-21Apr2011

Equations for VT calculation ©rlc L25-21Apr2011

Fully biased n-MOS capacitor VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y ©rlc L25-21Apr2011 L

MOS energy bands at Si surface for n-channel Fig 8.10** ©rlc L25-21Apr2011

Computing the D.R. W and Q at O.S.I. Ex Emax x ©rlc L25-21Apr2011

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** xd,max (mm) ©rlc L25-21Apr2011

Fully biased n- channel VT calc ©rlc L25-21Apr2011

n-channel VT for VC = VB = 0 Fig 10.20* ©rlc L25-21Apr2011

Fully biased p- channel VT calc ©rlc L25-21Apr2011

p-channel VT for VC = VB = 0 Fig 10.21* ©rlc L25-21Apr2011

n-channel enhancement MOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- n+ Depl Reg p-substrate Acceptors VB < 0 ©rlc L25-21Apr2011

Conductance of inverted channel Q’n = - C’Ox(VGC-VT) n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) The conductivity sn = (n’s/t) q mn G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’sqmnW) ©rlc L25-21Apr2011

Basic I-V relation for MOS channel ©rlc L25-21Apr2011

I-V relation for n-MOS (ohmic reg) ID non-physical ID,sat saturated VDS,sat VDS ©rlc L25-21Apr2011

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 ©rlc L25-21Apr2011

Computing the D.R. W and Q at O.S.I. Ex Emax x ©rlc L25-21Apr2011