ECAL OD Electronic Workshop 7-8/04/2005 TCC hardware test & commissioning plan M. Bercher, Y. Geerebaert, A. Karar, A. Mathieu, L. Zlatevski P. Busson, P. Paganini

TCC hardware test & commissioning plan TCC68 environment What is a TCC68 ? TCC68 Tests B.904 integration Conclusion

Trigger primitives @800 Mbits/s TCC68 environment OD TTC TCS Trigger Tower 25 Xtals (TT) Level 1 Trigger (L1A) L1 @100 kHz CCS (CERN) Regional CaloTRIGGER SLB (LIP) TCC (LLR) Global TRIGGER Trigger Tower Flags (TTF) Trigger primitives @800 Mbits/s SRP (CEA DAPNIA) Trigger Concentrator Card Synchronisation & Link Board Clock & Control System Selective Readout Processor Data Concentrator Card Timing, Trigger & Control Trigger Control System Selective Readout Flags (SRF) @100KHz (Xtal Datas) Data path DCC (LIP) DAQ From : R. Alemany LIP

What is a TCC68 P1 P0 P2 VME 9U Board 68(72) optical inputs @ 800 Mb/s => 1 supermodule (68 TT) 9 daughter boards SLB 6 optical receivers 12 channels 72 low-latency deserializers 6 FPGA (957 pins) 1 FPGA with integrated SerDes 1 TTCrx (Asic from CERN) Dedicated chip for Clock fanout 1 FPGA (VME64x «plug & play») PCB Design challenges : High interconnect density, high power consumption (~130W) Clean clock fanout (1:80) Aglient HDMP 1034A // Datas OD Connector XILINX FPGA Virtex2 pro Transciver E/O ALTERA FPGA for VME P0 Clock Fanout 1:90 P2 FromCCS TTCrx Chip To DCC To SRP

TCC68 (Trigger Concentrator Card 68 channels) Drawing report of TCC68 : PCB dim. 366 x 400 mm Thickness : 2,2 mm 10 layers Class 6 with µ-vias laser Controlled impedance vias 2734 components ~14000 connections ~14000 vias Etch length ~625 m

TCC68 (Trigger Concentrator Card 68 channels) Drawing report of TCC68 : PCB dim. 366 x 400 mm Thickness : 2,2 mm 10 layers Class 6 with µ-vias laser Controlled impedance vias 2734 components ~14000 connections ~14000 vias Etch length ~625 m

TCC68 prototype tests Tests carried out : Measure of power consumption VME interface Clock distribution Configuration at power on with new Flash from Xilinx (xcf32p). Reception of data via NGK receiver and Agilent deserialyzer Data bus from Xilinx to SLB via adaptation board (SLB_TLA) RocketIO, SFP link (under test) Tests remaining: RocketIO, SFP link OD interface TTCrx chip

Step 0:Check OD interface 9U VME64x CRATE L1A, CLK L1A, CLK 9U VME64x CRATE T C Ex/ VI C A E N C A E N D C C S T C L1A, CLK in the 6U slots TP: Trigger Primitives SRF: Selective Readout Flags TP SRF Crate Controller DAQkit V3 TTCvi/ex: generates clock and L1A S-Link64 pclip5 Need: 1 VME 9U Crate + controller with expected modification for power supply via Paux (=final OD crate) + OD back plane board 1 VME 9U crate + controller 1 DCC, 1 CCS, 1 TCC, 1 TTCvi+ex 1 (2?) PC TCC: at reception of L1A, it transmits patterns to DCC Patterns are previously loaded in TCC memories. DCC: Received patterns are checked using the PC

Step 0’:Check trigger interface 9U VME64x CRATE L1A, CLK L1A, CLK 9U VME64x CRATE T C Ex/ VI C A E N C A E N D C C S T C L1A, CLK in the 6U slots TP: Trigger Primitives SRPF: Selective Readout Flags TP Crate Controller DAQkit V3 S-Link64 STC/GCT pclip5 TTCvi/ex: generates clock and L1A Need: Step 0 + 1 STC/GCT + 9 SLBs TCC: At 40 MHz, it transmits patterns to STC via SLB Patterns are previously loaded in TCC memories. In this mode, nothing is transmitted to DCC (DCC not needed) STC/GCT: How does it check received patterns?

Step 1 : Check DCC datas @ L1A L1A, CLK L1A, CLK 9U VME64x CRATE 9U VME64x CRATE T C Ex/ VI D C - T C A E N C A E N D C C S T C L1A, CLK in the 6U slots DCC-T: DCC Tester TP: Trigger Primitives SRF: Selective Readout Flags TP SRF Crate Controller DAQkit V3 S-Link64 DCC-Tester: Generates clock and L1A signals for DCC pclip5 Need: Step 0 + 1 DCC-Tester + optical fibers TCC: At reception of L1A, it transmits patterns to DCC Patterns are previously loaded in TCC memories and must be consistent with what is sent by the DCC-Tester

Step 2 : Check DCC/TCC @ L1A L1A, CLK 9U VME64x CRATE 9U VME64x CRATE L1A, CLK T C Ex/ VI D C - T T C - C A E N C A E N D C C S T C L1A, CLK in the 6U slots DCC-T: DCC Tester TP: Trigger Primitives SRF: Selective Readout Flags TP TP SRF Crate Controller DAQkit V3 S-Link64 STC/GCT DCC-Tester: must have an input from TTCex Patterns loaded in DCC-Tester memories must be consistent with patterns loaded in TCC-Tester pclip5 TCC: Normal readout mode TCC-Tester: At 40 MHz, it transmits patterns to TCC Patterns are previously loaded in TCC-Tester memories. TCC-Tester generates the L1A and CLK, that are transmitted to TTCvi/ex and propagated to all the other boards Need: Step 1 + 1 TCC-Tester + optical fibers

Step 3 : Check SRP interface L1A, CLK 9U VME64x CRATE 9U VME64x CRATE L1A, CLK T C Ex/ VI D C - T T C - C A E N C A E N D C C S T C L1A, CLK in the 6U slots DCC-T: DCC Tester TP: Trigger Primitives SRF: Selective Readout Flags TP TP Crate Controller DAQkit V3 S-Link64 STC/GCT pclip5 SRF 6U VME CRATE Need: Step 2 + 1 AB board + optical fiber 1 SRP VME crate+ controller ? A B

B.904 integration Resources required in B.904 for TCC68 : 1 VME64x crate compatible with TCC68 power supply 1 OD Back plane 1 SBS crate controller (or CAEN ???) Cables with connectors such as BNC, SMA, etc… Optical fibers, optical couplers, etc… 1 “electronic” toolbox : Logic analyzer (Tektronix for probe compatibility with TCC68) Oscilloscope (freq. Min. 100 MHz, 2 or 4 channels, optical input ?) Clock generator (up to 50 MHz at least, 50 ohms, 2 outputs) + soldering iron, screw drivers, etc… 1 notebook and 1 PC4 (xilinx) to download firmware in TCC68 FPGAs A network connection, a printer, a coffee machine ?

TCC68 interfaces TCC68_V0 DCC CCS OD backplane LVDS@720Mb/s

TCC68 interfaces TCC68_V1 DCC CCS OD backplane LVDS@720Mb/s

TCC68 interfaces TCC68_V1 OD backplane DCC LVDS@720Mb/s

State of TCC : Conclusion Global architecture of TCC68 PCB seems to be OK We need lot of materials for B.904 We’d like to do some tests at CERN with SLB(s) on TCC68 before B.904 integration test. Which communication protocol for link with CCS ?