Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs Ian Kearney, Hank Sung, William Wolfe Device Analysis Services, Texas Instruments FemtoFETTM MOSFET Technology Ultra-small, low RDS(ON) power MOSFET transistor for space-constrained handheld applications.  package density & design consolidation.  power consumption & heat dissipation. Innovative LGA to reduce board space by up to 40% compared to CSP. Wafer TLP Test Results Type 2 Functional Failure Root Cause Lock-in Thermography Analysis : LSM Analysis: Type 2 failures confined to gate bus. Symmetrical land grid array packages in non socketed configurations have no balls and use a flat contact which is soldered directly to the PCB and BGA packages have balls as their contacts in between the IC and the PCBs Simulations: The first row of graphs in Fig. 19, gives gate voltage as a function of Rg, for a fixed Zener diode resistance (RDIODE). The second set of graphs increased RDIODE by five times (5X). The blue curve is a pin combination 1 event; the red curve is pin combination 2 event; the green curve represents the peak current value. Simulations demonstrated the benefit of adding a current limiting resistor (green curve) by lowering the voltage at the gate. The second row (Fig. 19) gives gate voltage versus diode resistance for two cases (1X and 30X). The gate oxide will be damaged if the diode on-resistance exceeds 10 ohms. The instantaneous power dissipation for pin combination 1 ranged from 36 watts (RDIODE = 1X) to 97.5 watts (R­DIODE = 25X). These values reduced by a factor of 1.5 to 3.5 when 30 ohms of gate ballasting resistance was introduced. Explicit n-well ballast resistors are often preferred due to the much lower sheet resistance compared to that of n+-diffusion. The observed parametric failures suggested the primary ESD protection elements needed more time to turn on. A current-limiting resistor would reduce this effect by (i) limiting the current flowing into the gate oxide, (ii) withstanding some ESD voltage, protecting the gate, and allowing sufficient time for the Zener shunt to respond. Tuning the N+ doping would allow a reduced slope on-resistance but the trade-off is increased leakage and lower breakdown voltage. This would increase device robustness against the observed soft failures. Assuming only charge injection, the amount of charge injected during the ESD event is very small (~0.6A * 100 ns = 6e-8 C per strike). However the simulations did not resolve the pin combination 1, negative ESD pulse, sensitivity. Type 1 Type 2 100ns TLP characteristic for Gate-Drain & Gate-source Package HBM Test Results Vt2,HBM = It2,TLP*RHBM Asymmetrical FemtoFETTM Chip Scale Package Design Post-Mortem VDG  in the vicinity of the poly-heads until TCRIT exceeded. Integrated ESD Protection WHY? A power MOSFET gate equivalent to a low voltage low leakage capacitor. Power MOSFET’s can have significant input capacitance producing a large spike in the ESD discharge current. Smaller devices  capacitance & require  charge per volt to reach a particular voltage  more susceptible to ESD. An ESD event between fingertip & communication-port connectors of a cell phone or tablet may cause permanent system damage. WHAT? Complete-static protection prevents static build-up & provides quick, reliable charge removal. HOW? Bi-directional diode active clamp. Provides 1.5 to 3.1 Amp continuous drain current. Why Asymmetrical Performance? Failure Classification Mechanical  handling Non-Functional parametric shift Functional Type 1 (clamp) & Type 2 VDG,VGS, IPK RDIODE 1X RDIODE 5X Mechanical RG 1X RG 30X Conclusion Pin sensitive Type 2 functional failures fixed by extending the p-body & thickening the epitaxial layer. Simulation demonstrated a current limiting resistor lowered the VGATE & delivered additional tturn-on. Type 1 Acknowledgements The authors wish to express gratitude to B Gillette, D Yencho, & W Ng for analysis support and B Davis for technical critique.