CR 245L Digital Design I Lab Sum of Products, 7-Segment Display, Schematic Capture II 2/1/2017 Prof. James Cavallo Bannow 133

Lab 3 – Top Level Diagram FPGA Control 7-Segment Logic Display (HEX0) SW0 SW1 Control Logic 7-Segment Display (HEX0) SW2 SW3

Seven Segment Display

Truth Table – Top Segment Decimal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 Segment Display Binary 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Top Segment 1

Sum of Products SW [3 .. 0] Top Segment [0] [1] [2] [3] INPUT – 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 [0] [1] [2] [3] INPUT – 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 [0] [1] [2] [3] [0] [1] [2] [3] .

Sum of Products Summary Identify each line in the truth table where the output is one. For each line where the output is one, apply the "and" function to all of the inputs, inverting the inputs that are zero, and directly connecting the inputs that are one. Apply the "or" function to the output of all of the and gates.

Lab 3 – Block Diagram FPGA Middle [6] Segment HEX0[6..0] SW[3..0] All Other Segments [5..0]

Part 1 – Step by Step Guide Create a folder on your desktop called “Lab 3”. Download the files provided from Blackboard, put them in the “Lab 3” folder that you just created, and extract any zip files. Launch Quartus II Create a new project called “lab3”. Be sure to point the Quartus software to the “Lab 3” folder that you just put onto your desktop, and be sure to select the EP4CE115F29C7 device from the Cyclone IV E family. Also, on the “Add Files” screen, add the files middle.bdf and all_others.vhd that have been provided. Create a new block diagram file, and save it as “lab3.bdf”. Insert an input pin named SW[3..0], and place it toward the left side of the screen. Insert an output pin named HEX0[6..0], and place it toward the right side of the screen. Compile the design. Map the pins. Go to assignments -> pin planner. Look up the pin locations in the document provided, and insert them in the table. Re-compile the design.

Part 2 – Step by Step Guide Insert the block “all_others”. Click on the symbol tool, and a new window will launch. Double click on the folder labeled “Project” in this window. Then click on the “all_others” item. The cursor will then turn into this block. Insert it somewhere in the lower - middle of the screen. Create a symbol for the middle segment. Click on the “files” tab in the pane in the top, left corner of the screen. Double click on the file middle.bdf. Click on File -> Create / Update -> Create Symbol Files for the Current File, and then click on Save. Insert the block “middle”. Follow a similar procedure to step 1 above to insert the block “middle” into the upper – middle part of the design. Connect the input “SW[3..0]” to the input “DIN[3..0]” on both the “all_others” and “middle” blocks. Connect the outputs “DOUT[5..0]” and “DOUT” of the blocks “all_others” and “middle” respectively to the output pin “HEX0[7..0]” as was demonstrated by the professor. Ask the professor if you need help.

Part 3 – Step by Step Guide Complete the truth table for the middle segment above. Complete the sum of products structure for the middle segment. Compile the design. Download the design to the DE2-115 board.

Truth Table Decimal 7 Segment Display Binary SW [3] [2] [1] [0] Middle 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1

7 – Segment Display

Lab 3 Assignment Show me a working circuit before you leave. Lab 3 will be graded on a pass / fail basis.