Test Sequence Length Requirements for Scan-based Testing

Slides:



Advertisements
Similar presentations
Operation Research Chapter 3 Simplex Method.
Advertisements

ADDITIONAL ANALYSIS TECHNIQUES LEARNING GOALS REVIEW LINEARITY The property has two equivalent definitions. We show and application of homogeneity APPLY.
Eigen-decomposition of a class of Infinite dimensional tridiagonal matrices G.V. Moustakides: Dept. of Computer Engineering, Univ. of Patras, Greece B.
THE ELIMINATION METHOD Solving Systems of Three Linear Equations in Three Variables.
CSE 373 Data Structures Lecture 15
Testimise projekteerimine: Labor 2 BIST Optimization
Digital Logic Lecture 4 Binary Codes The Hashemite University Computer Engineering Department.
ΑΡΙΘΜΗΤΙΚΕΣ ΜΕΘΟΔΟΙ ΜΟΝΤΕΛΟΠΟΙΗΣΗΣ 4. Αριθμητική Επίλυση Συστημάτων Γραμμικών Εξισώσεων Gaussian elimination Gauss - Jordan 1.
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Adviser :蔡亮宙 Student ;蔡政宏.
December, 2004 Ecole Polytechnique 1 Deterministic BIST By Amiri Amir Mohammad Professor Dr. Abdelhakim Khouas Project Presentation for ELE6306 (Test des.
Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,
Weikang Qian. Outline Intersection Pattern and the Problem Motivation Solution 2.
TOPIC : Signature Analysis. Introduction Signature analysis is a compression technique based on the concept of (CRC) Cyclic Redundancy Checking It realized.
Sorting and Searching by Dr P.Padmanabham Professor (CSE)&Director
Data and Knowledge Engineering Laboratory Clustered Segment Indexing for Pattern Searching on the Secondary Structure of Protein Sequences Minkoo Seo Sanghyun.
Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.
Law of Variable Proportions
Solving Linear Systems by Substitution
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Wei-Cheng Lien 1, Kuen-Jong Lee 1 and Tong-Yu.
Page Buffering, I. Pages to be replaced are kept in main memory for a while to guard against poorly performing replacement algorithms such as FIFO Two.
2D-LDA: A statistical linear discriminant analysis for image matrix
Chapter 9: Sorting1 Sorting & Searching Ch. # 9. Chapter 9: Sorting2 Chapter Outline  What is sorting and complexity of sorting  Different types of.
Huffman Coding (2 nd Method). Huffman coding (2 nd Method)  The Huffman code is a source code. Here word length of the code word approaches the fundamental.
OBJ: Solve Linear systems graphically & algebraically Do Now: Solve GRAPHICALLY 1) y = 2x – 4 y = x - 1 Do Now: Solve ALGEBRAICALLY *Substitution OR Linear.
WARM-UP. SYSTEMS OF EQUATIONS: ELIMINATION 1)Rewrite each equation in standard form, eliminating fraction coefficients. 2)If necessary, multiply one.
Introduction to Algorithms: Brute-Force Algorithms.
3.5 Solving systems of equations in three variables Main Ideas Solve systems of linear equations in three variables. Solve real-world problems using systems.
Simultaneous Equations 1
EMGT 6412/MATH 6665 Mathematical Programming Spring 2016
WARM UP Find each equation, determine whether the indicated pair (x, y) is a solution of the equation. 2x + y = 5; (1, 3) 4x – 3y = 14; (5, 2)
Computer Organization and Architecture + Networks
Subject Name: File Structures
Ioannis E. Venetis Department of Computer Engineering and Informatics
Data Structures Using C++ 2E
Updating SF-Tree Speaker: Ho Wai Shing.
Modeling with Recurrence Relations
CSE15 Discrete Mathematics 03/13/17
UNIVERSITY OF MASSACHUSETTS Dept
Numerical Analysis Lecture12.
Chapter 11: File System Implementation
Data Structures Using C++ 2E
Review Graph Directed Graph Undirected Graph Sub-Graph
VLSI Testing Lecture 14: Built-In Self-Test
Improving cache performance of MPEG video codec
Hash Table.
Chapter 11: File System Implementation
Registered Electrical & Mechanical Engineer
Chapter 3 The Simplex Method and Sensitivity Analysis
Lecture 3: Main Memory.
Matrix Solutions to Linear Systems
Numerical Analysis Lecture14.
Dynamic Programming and Applications
Numerical Analysis Lecture13.
Sungho Kang Yonsei University
COMP60621 Fundamentals of Parallel and Distributed Systems
Numerical Analysis Lecture10.
Solving Equations 3x+7 –7 13 –7 =.
ECE 352 Digital System Fundamentals
MS Thesis Defense Presentation by Mustafa Imran Ali COE Department
Chapter 11: File System Implementation
Reseeding-based Test Set Embedding with Reduced Test Sequences
Test Data Compression for Scan-Based Testing
INTRODUCTION TO ALOGORITHM DESIGN STRATEGIES
COMP60611 Fundamentals of Parallel and Distributed Systems
Operating Systems: Internals and Design Principles, 6/E
Error Correction Coding
Chapter5: Synchronous Sequential Logic – Part 3
Cryptography Lecture 15.
Multiply by 5/40 and sum with 2nd row
ADDITIONAL ANALYSIS TECHNIQUES
Presentation transcript:

Test Sequence Length Requirements for Scan-based Testing An Efficient Test Set Embedding Scheme with Reduced Test-Data Storage and Test Sequence Length Requirements for Scan-based Testing D. Kaseridis1, E. Kalligeros1, X. Kavousianos2 & D. Nikolos1 2Dept. of Computer Science University of Ioannina, 45110, Ioannina, Greece 1Dept. of Computer Engineering & Informatics University of Patras, 26500, Patras, Greece e-mails: kaserid@ceid.upatras.gr, kalliger@ceid.upatras.gr, kabousia@cs.uoi.gr, nikolosd@cti.gr I. Test set Embedding Core-oriented way of designing contemporary SoCs leads to larger and denser circuits that require greater test data volumes and longer test-application times The introduction of new, embedded testing solutions that overcome these problems is of great importance. Test set embedding techniques that combine both reduced hardware and test-data storage requirements with short test sequences are desirable II. Seed Selection Algorithm We consider the classical LFSR-based reseeding scheme: LFSR, Bit and Vector Counter The algorithm receives as input the size L of the window (number of test-vectors) that each seed expands to and a set of test cubes T For determining a new seed the seed-algorithm makes uses of the well-known concept of solving systems of linear equations (i.e. assuming Gauss-Jordan elimination) The algorithm examines all possible linear systems and chooses one to solve Table1. Seed-selection algorithm's criteria Criterion Description 1st Select the solvable systems that corresponds to the test cubes containing the maximum number of defined bits 2nd If there are more than one solvable systems selected by the 1st criterion, choose the solvable system that its solution leads to the replacement of the fewest variables ai in the L-vector window 3rd If there are more than one solvable systems selected by the 2nd criterion, select the solvable system that is nearest to the first vector of the window Since at each step of algorithm, linear systems corresponding to more than one test cubes will be solvable at more than one positions of the window, a set of heuristics is used (Table 1) for selecting the system that will be actually solved III. Test-sequence reduction scheme Seed-selection algorithm assumes a window of L successive test vectors for each selected seed. (Fig. 1) If the last vector of a window is not a useful one then all vectors from the last useful one to the last vector of each window are redundant Rearrangement technique Main idea: Order the seeds according to the number of useful segments If these volumes for every two successive windows differs at most by one  Only a single extra bit per seed is needed for indicating this relation. Extra bit=0  Same number of useful segment Extra bit=1  One segment difference Example of rearrangement technique Fig. 1. A window of L stages Proposed window segmentation approach Each window is segmented into a number (m) of equal-sized groups of test vectors (Fig. 2) The useful vectors of the window are included in the first k segments and thus the remaining m-k segments contain redundant test vectors and can be dropped during test generation Load Counter: Down counter that maintains the necessary number of segments for each window Bit Counter: controls the scan-in operation of each vector's bits Segment-Vectors Counter: controls the generation of the test vectors of a single segment Segment Counter: counts for the required number of segments for each window and is initialized for each seed with the value of Load Counter Fig. 2. The proposed window segmentation technique Fig. 3. The proposed test-sequence reduction scheme IV. Comparisons The proposed approach compares favorably against the most recent and efficient test set embedding technique in the literature (Reconfigurable Interconnection Networks–TCAD’04) The comparison shows that the proposed scheme requires substantially smaller test sequences (Fig. 4) and hardware overhead (Fig. 5) for both 32 () and 64 () scan chains Fig. 4. Test sequence length reductions Fig. 5. Hardware overhead reductions