EE 445S Real-Time Digital Signal Processing Lab Spring 2017 Lab #2 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6748 DSP (Continued) Debarati Kundu and Sam Kanawati (with the help of Mr. Eric Wilbur, TI) 1 1

EDMA Idea is that, with EDMA, CPU can initiate data transfer and do other operations while transfer is in progress. More efficient than using regular I/O which keeps CPU occupied during entire transfer. EDMA controller: Handles all data transfers between L2 cache and peripherals. Can move data to and from any addressable memory spaces (internal memory, external memory and peripherals) independently of CPU operations. 2

C674x DSP Block Diagram

EDMA Features Has 64 channels that can be assigned priorities. EDMA3 needs: Source Address Destination Address Size of transfer After an element transfer, addresses at source/destination can stay the same, get incremented or decremented. Data transfers can be initiated by CPU or events (such as the McASP FIFO buffers full). Programmable Transfer Burst Size: Transfers can be 8-bit bytes, 16-bit half-words, or 32-bit words. Can transfer 2-dimensional data blocks. 4

EDMA Features When an event occurs its transfer parameters are read from the Parameters RAM (PaRAM) and then sent to the address generation hardware. After a programmed transfer, EDMA can continue transfers by linking to another transfer programmed in the PaRAM for same channel, or chaining to a transfer for another channel Can generate transfer completion interrupts to the CPU along with a transfer complete code, for it to take desired action based on that code. EDMA has a Quick DMA mode (QDMA) for quick, one- time transfers. 5

EDMA Channel Controller Block Diagram

EDMA3 Terminology 3-dimensional transfer consisting of ACNT, BCNT and CCNT: Element = The smallest unit of a DMA transfer. An element can be 8-bit, 16-bit, or 32-bit. ACNT = Array = A group of contiguous elements comprise an array BCNT = Frame = A group of elements comprise a frame. CCNT = Block = A group of arrays or frames form a block. Minimum transfer is an array of ACNT bytes Total transfer count = ACNT * BCNT * CCNT Frame 1 ACNT Bytes Array1 Array2 Array BCNT Frame 2 Frame CCNT CCNT Frames BCNT Arrays 7

Example – How do you VIEW the transfer? We need to transfer 12 bytes from “here” to “there”. 8-bit Note: these are contiguous memory locations What is ACNT, BCNT and CCNT? You can “view” the transfer several ways: ACNT = 1 BCNT = 4 CCNT = 3 ACNT = 2 BCNT = 2 CCNT = 3 ACNT = 12 BCNT = 1 CCNT = 1 Which “view” is the best? Well, that depends on what your system needs and the type of synchronization…

EDMA Channel/Parameter RAM Sets EDMA3 has 256 Parameter RAM sets (PSETs) that contain configuration information about a transfer 64 DMA CHs and 4 QDMA CHs can be mapped to any one of the 256 PSETs and then triggered to run (by various methods) 64 DMA CHs PaRAM Set 0 PaRAM Set 1 . . . . 63 PSET 63 4 QDMA CHs PSET 64 . . . . PSET 255 3 Note: PSETs are dedicated EDMA RAM (not part of IRAM)

“A” – Synchronization An event (like the McBSP receive register full), triggers the transfer of exactly 1 array of ACNT bytes (2 bytes) Example: McBSP tied to a codec (you want to sync each transfer of a 16-bit word to the receive buffer being full or the transmit buffer being empty). EVTx EVTx EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT 12

“AB” – Synchronization An event triggers a two-dimensional transfer of BCNT arrays of ACNT bytes (A*B) Example: Line of video pixels (each line has BCNT pixels consisting of 3 bytes each – Y, Cb, Cr) EVTx Frame 1 Array1 Array2 Array BCNT Frame 2 Array1 Array2 Array BCNT Frame CCNT Array1 Array2 Array BCNT 13

EDMA Event Processing Registers: Event Register (ER): when event n occurs, bit n of ER is set. Event Enable Register (EER): setting bit n of EER enables processing of that event. Event Clear Register (ECR): setting a bit in ECR clears corresponding bit in ER, used by CPU to clear event flags. Event Set Register (ESR): setting a bit in ESR sets corresponding bit in ER, used by CPU to submit event requests and for debugging. 14

EDMA Interrupt Generation Generate EDMA Interrupt (Setting IERbit) EDMA Channels EDMA Interrupt Generation Channel # Options TCC IPR IER TCINTEN=0 TCC=0 IER0 = 0 1 TCINTEN=0 TCC=1 IER1 = 0 EDMA3CC_GINT . 1 TCINTEN=1 TCC=14 IER14 = 1 63 TCINTEN=0 TCC=63 IER63 = 0 Options TCINTEN TCC IER – EDMA Interrupt Enable Register (NOT the CPU IER) IPR – EDMA Interrupt Pending Register (set by TCC) 20 17 12 Use EDMA3 Low-Level Driver (LLD) to program EDMA’s IER bits

Linking Needed when we want to repeat the transfer Linking two or more channels together allows the EDMA to auto-reload a new configuration when the current transfer is complete Linking still requires a trigger to start the transfer (manual, chain, or event) We can link as many PSETs as we like, limited only by the number of PSETs on a device.

Chaining Needed When one transfer completes, trigger another transfer to run (for example, Ch0 completes, kicks off Ch1) Chaining actually refers to both an action and an event – the completed ‘action’ from the 1st channel is the ‘event’ for the next channel We can chain as many channels as we like, only limited by the channels on a device Chaining does NOT reload current channel configuration– that can only be accomplished by linking. It simply triggers another channel to run.