Depletion depth studies of HV-CMOS detectors Stewart Laroche Supervisors: Daniel Muenstermann, Michael Moll, and Christian Gallrapp

Project Goals Investigate HV-CMOS silicon technology for use as detectors Cheap to produce, with wide variety of manufacturers High resolution (25x25 um pixels) Radiation hard CMOS technologies also allow for onboard amplification and discriminators, allows for better resolution Due to even greater fluences in upgraded LHC, radiation hardness is of great concern. HV-CMOS detectors look promising. Acceptor removal in p-substrate may actually lead to better performance after irradiation (for limited fluence)

My Project Use Edge-TCT testing to determine depletion depth Determine IV curves for different biasing structures Analyze wide range of samples (fluence, resistivity, biasing) Possibly improve detector’s PCB design using PCB-CAD software

Progress While my supervisors were at an RD-50 meeting in Spain, I helped Daniel Hynds characterize his HV-CMOS detectors with CLICpix readout chips The readout chips are capacitively bonded to the pixel matrix Tests focused on finding the response of the pixels as the laser intensity was changed I became familiar with the setup and software, so I am prepared to begin eTCT testing Better understanding of HV-CMOS detectors

Beyond CERN Hiking Saléve Climbing at Lac Léman Fete de la Musique The amazing food and wine! The wonders of the Swiss health care system