Christophe Beigbeder PID meeting

Slides:



Advertisements
Similar presentations
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
Advertisements

Readout ASIC for SiPM detector of the CTA new generation camera (ALPS) N.Fouque, R. Hermel, F. Mehrez, Sylvie Rosier-Lees LAPP (Laboratoire d’Annecy le.
L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.
1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN.
SKIROC ADC measurements and cyclic ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting Orsay June.
Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C.
Status of the PSD upgrade - Status of the PSD cooling and temperature stabilization system - MAPD gain monitoring system - PSD readout upgrade F.Guber,
Juin 1st 2010 Christophe Beigbeder PID meeting1 PID meeting Electronics Integration.
Mai 31th 2011 Christophe Beigbeder PID meeting1 ETD meeting Test setup : Activities in Bari, Univ of Maryland and at Orsay Test setup : Activities in Bari,
PArISROC Photomultiplier Array Integrated in Sige Read Out Chip Selma Conforti Frédéric Dulucq Christophe de La Taille Gisèle Martin-Chassard Wei
Christophe Beigbeder - SuperB meeting - SLAC Oct PID electronics summary electronics (on behalf of PID electronics group)
PHOTOTUBE SCANNING SETUP AT THE UNIVERSITY OF MARYLAND Doug Roberts U of Maryland, College Park.
1 D. BRETON 1, L.LETERRIER 2, V.TOCUT 1, Ph. VALLERAND 2 (1) LAL ORSAY - France (2) LPC CAEN - France Super Nemo Absolute Time Stamper A high resolution.
Week 22: Schematic Week 23-Week 27: Routing Gerber files have been available since 9th July 1st prototype: – PCB manufacturer: supervised by KIT – Cabling:
C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.
J.Maalmi, D.Breton – SuperB Workshop – Frascati – September 2010 Electronics for the two-bar test. D.Breton & J.Maalmi (LAL Orsay)
1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting London 2008.
SKIROC status Calice meeting – Kobe – 10/05/2007.
Tuesday, 20 May 2003OPERA Collaboration Meeting - Gran Sasso1 Status of front-end electronics for the OPERA Target Tracker LAL Orsay S.BONDIL, J. BOUCROT,
Status of front-end electronics for the OPERA Target Tracker
PADME Front-End Electronics
Work on Muon System TDR - in progress Word -> Latex ?
"North American" Electronics
DAQ (i.e electronics) R&D status in Canada
ETD meeting Architecture and costing On behalf of PID group
A 12-bit low-power ADC for SKIROC
Front-end Electronic for a neutrino telescope : a new ASIC SCOTT
Pid session TDC-based electronics for the CRT
ETD PID meeting We had many presentations dedicated to the PM test .
V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
Christophe Beigbeder PID meeting
ASIC PMm2 Pierre BARRILLON, Sylvie BLIN, Selma CONFORTI,
Tracker TriP-t Test Stand
CTA-LST meeting February 2015
Electronics for FTOF prototype: status of the 16-ch WaveCatcher board D.Breton & J.Maalmi (LAL Orsay) …
Alternative FEE electronics for FIT.
Designing electronics for a TOF Forward PID for SuperB D. Breton & J
R&D activity dedicated to the VFE of the Si-W Ecal
ETD meeting Electronic design for the barrel : Front end chip and TDC
From SNATS to SCATS C. Beigbeder1, D. Breton1,F.Dulucq1, L. Leterrier2, J. Maalmi1, V. Tocut1, Ph. Vallerand3 1 : LAL Orsay, France (IN2P3 – CNRS) 2 :
PID meeting SCATS Status on front end design
Update of time measurement results with the USB WaveCatcher board & Electronics for the DIRC-like TOF prototype at SLAC D.Breton , L.Burmistov,
Christophe Beigbeder PID meeting
DCH FEE 28 chs DCH prototype FEE &
L. Ratti, M. Manghisoni Università degli Studi di Pavia INFN Pavia
Hugo França-Santos - CERN
Front-end electronics Bis7-8
MCPPMT test bench at LAL D. Breton, L. Burmistov, J. Maalmi, V
Ongoing R&D in Orsay/Saclay on ps time measurement: a USB-powered 2-channel 3.2GS/s 12-bit digitizer D.Breton (LAL Orsay), E.Delagnes (CEA/IRFU) Séminaire.
Using ultra fast analog memories for fast photo-detector readout D
TDC at OMEGA I will talk about SPACIROC asic
CALICE COLLABORATION LPC Clermont LAL Orsay Samuel MANEN Julien FLEURY
Muon Recording Studies and Progress for the MICE Tracker
Christophe Beigbeder/ PID meeting
Christophe Beigbeder/ ETD PID meeting
EUDET – LPC- Clermont VFE Electronics
Christophe de La Taille * Gisèle Martin-Chassard *
CLAS12 Timing Calibration
PID electronics for FDIRC (Focusing Detector of Internally Reflected Cherenkov light) and FTOF (Forward Time of Flight) Christophe Beigbeder and Dominique.
SKIROC status Calice meeting – Kobe – 10/05/2007.
HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)
HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)
Signal processing for High Granularity Calorimeter
V. Tocut, LAL/IN2P3 Orsay H. Lebbolo LPNHE/IN2P3 Paris
PID meeting Mechanical implementation Electronics architecture
Presented by T. Suomijärvi
Ongoing R&D in Orsay/Saclay on ps time measurement: status of the USB-powered 2-channel 3.2GS/s 12-bit digitizer D.Breton & J.Maalmi (LAL Orsay), E.Delagnes.
Electronics for the PID
Orsay Talks Christophe : General questions and future developments.
Presentation transcript:

Christophe Beigbeder PID meeting 10 SCATS has been delivered in February, one month earlier than expected ! 5 are for each of the two labs, LAL and LPC Caen. Both LPC Caen and LAL are designing test boards. LPC design a daughter board to adapt there existing test setup to SCATS. LAL is designing 2 digital boards : one for the test of the SCATS and one for the CRT module. ->First one expected mid April. Two analog boards was delivered last month at LPNHE PIF : design has started with simulations. ANR for FDIRC and FTOF has been submitted by Nicolas, asking for 1M€ Christophe Beigbeder PID meeting March 21 th 2012

Scats test board General synoptic of SCATS test board

Scats test board Functional synoptic of FPGA used in SCATS test board

Test board: elements of firmware Raw data are stored in a evt FIFO. Next step : implementation of the evt buffer. One Hit generator per channel : Min time between hits : 12.5 ns Max time ~ 1.6 us Christophe Beigbeder

Scats test board The figure below show the current PCB status

PIF : a design test for SCATS Analog pipeline : could be skipped in the first version for time and cost reasons Discriminator and charge amplifier This schema is well adapted to be tested in a standalone mode or with SCATS in low input rate condition for synchronization problems

 Delay + Fraction  Gain + Integrators CFD on silicon Fast comparator Classical CFD Proposed pseudo CFD Delay + Fraction  Gain + Integrators

Spice Simulations

Simulations with AMS CMOS 0.35µ

Simulations with AMS CMOS 0.35µ Input signal Amplified Integration Difference between amplified signal and delayed amplified signal

Parametric simulation : amplitude from 1 to 10 45ps walk Resolution: 50ps for a dynamic of 10

PIF design : Charge amplifier simulations Simulation schematic used for ampli_00

Out_ampli00 response with input pulse amplitude 10mV to 50 mV Ampli_00 Output amplitude linearity

Out_ampli00 response with input pulse amplitude 1mV to 60 mV Output amplitude input signal 100 MHz Saturation effect on max values Output amplitude input signal 1 MHz No saturation effect on max values

Analog Board Received 1month ago . The first burnt and we received last week a new one

Analog board : first result Input signal  ~ 10 mv on 50 Ohm per single pe to be confirmed on our PM test setup Noise to be studied Discri output : has to be connected to a latch input for fine measurements Gain , CFD fraction & delay , pseudo CFD integration has to be adjusted Christophe Beigbeder

Next step @ schedule Tests of the analog board at the LPNHE Test the analog board using the PM test setup at LAL Design of the test board will be finished end of Mars Firmware and software : to be developed in Orsay ( already started) and Bari ( ? ) Test of the SCTATS at LAL and LPC Caen as soon as the board ready Simulation and design of the PIF continue. Submission probably shifted to end of this year. Christophe Beigbeder