Christophe Beigbeder PID meeting 10 SCATS has been delivered in February, one month earlier than expected ! 5 are for each of the two labs, LAL and LPC Caen. Both LPC Caen and LAL are designing test boards. LPC design a daughter board to adapt there existing test setup to SCATS. LAL is designing 2 digital boards : one for the test of the SCATS and one for the CRT module. ->First one expected mid April. Two analog boards was delivered last month at LPNHE PIF : design has started with simulations. ANR for FDIRC and FTOF has been submitted by Nicolas, asking for 1M€ Christophe Beigbeder PID meeting March 21 th 2012

Scats test board General synoptic of SCATS test board

Scats test board Functional synoptic of FPGA used in SCATS test board

Test board: elements of firmware Raw data are stored in a evt FIFO. Next step : implementation of the evt buffer. One Hit generator per channel : Min time between hits : 12.5 ns Max time ~ 1.6 us Christophe Beigbeder

Scats test board The figure below show the current PCB status

PIF : a design test for SCATS Analog pipeline : could be skipped in the first version for time and cost reasons Discriminator and charge amplifier This schema is well adapted to be tested in a standalone mode or with SCATS in low input rate condition for synchronization problems

 Delay + Fraction  Gain + Integrators CFD on silicon Fast comparator Classical CFD Proposed pseudo CFD Delay + Fraction  Gain + Integrators

Spice Simulations

Simulations with AMS CMOS 0.35µ

Simulations with AMS CMOS 0.35µ Input signal Amplified Integration Difference between amplified signal and delayed amplified signal

Parametric simulation : amplitude from 1 to 10 45ps walk Resolution: 50ps for a dynamic of 10

PIF design : Charge amplifier simulations Simulation schematic used for ampli_00

Out_ampli00 response with input pulse amplitude 10mV to 50 mV Ampli_00 Output amplitude linearity

Out_ampli00 response with input pulse amplitude 1mV to 60 mV Output amplitude input signal 100 MHz Saturation effect on max values Output amplitude input signal 1 MHz No saturation effect on max values

Analog Board Received 1month ago . The first burnt and we received last week a new one

Analog board : first result Input signal  ~ 10 mv on 50 Ohm per single pe to be confirmed on our PM test setup Noise to be studied Discri output : has to be connected to a latch input for fine measurements Gain , CFD fraction & delay , pseudo CFD integration has to be adjusted Christophe Beigbeder

Next step @ schedule Tests of the analog board at the LPNHE Test the analog board using the PM test setup at LAL Design of the test board will be finished end of Mars Firmware and software : to be developed in Orsay ( already started) and Bari ( ? ) Test of the SCTATS at LAL and LPC Caen as soon as the board ready Simulation and design of the PIF continue. Submission probably shifted to end of this year. Christophe Beigbeder