Advanced Computer Architecture Lecture 14 Project 4 review Write-back cache correction Write buffer Performance Lillevik 437s06-l14 University of Portland School of Engineering
Project 4 team review Team Dog Lillevik 437s06-l14 University of Portland School of Engineering
Cache block diagram R/W# Main Driver System enable Bus Control enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Find types of cache in PC? Memory CPU End of a bus Veda, sound, net DMA Wireless, CD, HD Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, cache hit Read Write Data provided by cache memory Fast Data written to cache (fast) Data NOT written to memory, inconsistency exists Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, cache miss Two cases Memory and cache consistent Memory and cache inconsistent (cache has correct data) Called modified Called dirty All misses to inconsistent cache and memory require a write-back cycle first Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, read miss Cache consistent Cache inconsistent Data provided by main memory (slow) Data also written to cache (update) Cache inconsistent Data in cache written to memory (slow): WB Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, write miss Cache consistent Cache inconsistent Data written to cache (fast) Data NOT written to memory, inconsistency exists Cache inconsistent Data in cache written to memory (slow): WB Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, read hit R/W# Main Driver System enable Bus Control enable Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, write hit R/W# Main Driver System enable Bus Control Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, read miss Memory consistent R/W# Main Driver System enable Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, read miss Two steps: write-back and memory read Memory inconsistent Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, write miss Memory consistent R/W# Main Driver System Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write-back, write miss? Two steps: write-back and write cache Memory inconsistent Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Cache example CPU: our B2Logic model Memory of 32 words Cache of 8 words Direct mapped Cache and memory at an initial state Lillevik 437s06-l14 University of Portland School of Engineering
Initial memory contents Adr Data 1 2 3 4 5 6 7 8 9 A B C D E F Adr Data 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Cache Indexb Tagb Data 000 10 001 01 09 010 0A 011 13 100 0C 101 15 110 11 1E 111 17 Lillevik 437s06-l14 University of Portland School of Engineering
Complete the table? Instruction Tagb Indexb Hit type Data 51700 10 111 RH 17 60955 50F00 611AA 50900 51C00 6145A 51100 602A5 Lillevik 437s06-l14 University of Portland School of Engineering
Final memory contents? Memory Cache Adr Data Adr Data Indexb Tagb Data 1 2 3 4 5 6 7 8 9 55 A B C D E F Adr Data 10 11 aa 12 13 14 5a 15 16 17 18 19 1A 1B 1C 1D 1E 1F Cache Indexb Tagb Data 000 001 01 55 010 011 100 10 5a 101 110 111 0f Lillevik 437s06-l14 University of Portland School of Engineering
Write-through write hit SLOW !! Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik 437s06-l14 University of Portland School of Engineering
Write buffer Goal: speed up writes to memory Design Add write buffer (register) between cache and memory Once register written, Ack CPU Write to memory overlaps next instruction, hides memory access time Design Register often a FIFO Typical depth of 4 lines Lillevik 437s06-l14 University of Portland School of Engineering
Write buffer, write hit (or miss) Write-through cache Write buffer, write hit (or miss) Main Cache Control Driver enable R/W# tag System Bus Buffer Lillevik 437s06-l14 University of Portland School of Engineering
Memory write overlaps next instruction Write buffer timing 1st write 2nd write read hit CPU Ack R/W# 1st write 2nd write Memory write overlaps next instruction Lillevik 437s06-l14 University of Portland School of Engineering
Memory performance Metrics: latency, bandwidth Average latency, L Assumes cache latency same for reads and writes Expression may be applied recursively Lillevik 437s06-l14 University of Portland School of Engineering
Find average latency? CPU clocked at 1.5 GHz DDR memory speed is 500 MHz Cache cycle time is 100 ps Hit rate is 0.95 Lillevik 437s06-l14 University of Portland School of Engineering
Write buffer performance Write-through cache Write buffer performance Reads: occur with probability r Writes: occur with probability (1-r) Four possibilities (probabilities) RH = rh = cache hit, Lc RM = r(1-h) = cache miss, Lm WH = (1-r)h = cache hit, Lc WM = (1-r)(1-h) = cache hit, Lc Due to buffer Lillevik 437s06-l14 University of Portland School of Engineering
Find write buffer performance? Lillevik 437s06-l14 University of Portland School of Engineering
Find average latency? Direct mapped cache, write buffer CPU clocked at 1.5 GHz DDR memory speed is 500 MHz Cache cycle time is 100 ps Hit rate is 0.95 One write to every three reads Lillevik 437s06-l14 University of Portland School of Engineering
Lillevik 437s06-l14 University of Portland School of Engineering
Find types of cache in PC? Memory: L1, L2 (data and instruction) Hard drive CD drive Modem, Ethernet controller Graphics controller Serial, parallel port, USB Printer Lillevik 437s06-l14 University of Portland School of Engineering
Find average latency? Lillevik 437s06-l14 University of Portland School of Engineering
Find write buffer performance? Lillevik 437s06-l14 University of Portland School of Engineering
Find average latency? Lillevik 437s06-l14 University of Portland School of Engineering