EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 1 Ramzan Mat Ayub; SATF 2005 EMT362: Microelectronic Fabrication CMOS ISOLATION TECHNOLOGY Part 1 Ramzan Mat Ayub School of Microelectronic Engineering

Lecture Objectives Understand the basic operation of MOS Capacitor Ramzan Mat Ayub; SATF 2005 Lecture Objectives Understand the basic operation of MOS Capacitor Able to calculate the Threshold Voltage for MOS Capacitor and Transistor Understand why isolation is needed in CMOS process Understand the isolation requirements and related design rules Able to describe in terms of wafer cross section, the process steps for Semirecessed LOCOS, Fully Recessed LOCOS, STI and several advanced isolation structures formation.

Standard CMOS Process Flow Ramzan Mat Ayub; SATF 2005 Standard CMOS Process Flow Main Process Modules (CMOS 1P2M 3.3V) Wells Formation Active Area Definition Device Isolation (LOCOS) Vt Adjust Polygate Definition Source & Drain Formation Pre Metal Dielectrics Deposition (PMD) Contact Definition Metal-1 Deposition & Patterning Inter-Metal Dielectrics Deposition (IMD) Via Definition Metal-2 Deposition & Patterning Passivation Pad Definition FRONT END PROCESS (creating an electrically isolated devices) BACK END PROCESS (connecting the devices to form the desired circuit function.) Full integration may require 300-500 process steps

Ideal MOS Capacitor Basic Structure Metal Insulator Semiconductor Ramzan Mat Ayub; SATF 2005 Ideal MOS Capacitor Basic Structure Metal Insulator Semiconductor

Energy Band Diagram for Ideal MOS capacitor Ramzan Mat Ayub; SATF 2005 Energy Band Diagram for Ideal MOS capacitor No external bias, V=0 Work function – energy required to remove an electron from fermi level to outside of the material. Ec In ideal case, assume Ei EFm EFs Ev Metal Oxide P-type s-conductor

The shift in EFm causes a tilt in the oxide conduction band. Ramzan Mat Ayub; SATF 2005 E V < 0 Accumulation Ec EFm q V Ei EFs Ev Negative charge deposited on the metal, in response an equal amount of positive charge will accumulate at the surface of s-conductor. In the case of p-type s-c, this is called hole accumulation. Due to the raise of electron energies in metal, Efm increases from equilibrium position by q V The shift in EFm causes a tilt in the oxide conduction band. The energy bands of s-c bend near the interface to accommodate the accumulation of holes.

uncompensated ionized acceptors. Ramzan Mat Ayub; SATF 2005 E Depletion V > 0 Ec Ei EFs Ev q V EFm Positive charge deposited on the metal, holes will be drived away from the surface, leaving behind uncompensated ionized acceptors. Due to the raise of holes energies in metal, Efm decreases from equilibrium position by q V The shift in EFm causes a tilt in the oxide conduction band. The energy bands of s-c bend near the interface to accommodate the depletion of holes. Maximum depletion region width

to the MOS transistor operation. Ramzan Mat Ayub; SATF 2005 V > > 0 E Inversion - - - Ec Ei EFs Ev q V EFm If the positive bias is increased, s-c energy bands bend further i.e more holes depleted away. At certain voltage, Ei can bend below Efs, implied that a large concentration of electron at the s-c surface. In this case, the region at the s-c surface has a conduction properties typical to the n-type s-c. This inverted layer, separated from the underlying p-type substrate by a depletion region is they key to the MOS transistor operation.

The strong inversion condition is defined when Ramzan Mat Ayub; SATF 2005 V > > 0 Ec Ei EFs Ev The strong inversion condition is defined when

Threshold Voltage of MOS Capacitor Ramzan Mat Ayub; SATF 2005 Threshold Voltage of MOS Capacitor To reach strong inversion condition To reach maximum depletion width where

Calculate the maximum width of the depletion region for an ideal MOS Ramzan Mat Ayub; SATF 2005 Example 1 Calculate the maximum width of the depletion region for an ideal MOS capacitor on p-type Si with NA=1015 atoms/cm3 Q4, Tutorial 1

Ramzan Mat Ayub; SATF 2005 Example 2 Using the conditions in example 1, with 1000A –thick SiO2 layer, calculate the threshold voltage of this capacitor. Given the dielectric constant for SiO2 is 3.9 VT = 0.98 V Q5, Tutorial 1

Threshold Voltage of MOS Transistor Ramzan Mat Ayub; SATF 2005 Threshold Voltage of MOS Transistor The threshold voltage of a MOSFET is defined as the gate voltage where an inversion region forms at the surface of the transistor’s channel. VG VG = VT VD VD n+ n+ n+ n+ p-well p-well VB = 0 VB = 0

2 additional factors in VT calculation; Ramzan Mat Ayub; SATF 2005 2 additional factors in VT calculation; Work function difference between Al and Si (caused band bending) SiO2-Si interface Charge (caused band bending)

Energy Band Diagram for MOS Transistor Ramzan Mat Ayub; SATF 2005 Energy Band Diagram for MOS Transistor No external bias, V=0 Ec Ei EFm EFs Ev Metal Oxide P-type s-conductor

Ec Ei q V EFm EFs Flatband Condition V = VFB = Ramzan Mat Ayub; SATF 2005 Ec Ei q V EFm EFs Flatband Condition V = VFB =

Metal SiO2 SiOx Semi-conductor + + + + + + - - - - - Ramzan Mat Ayub; SATF 2005 Metal SiO2 SiOx Semi-conductor + + + + + + - - - - - Flatband Condition V = VFB

Ramzan Mat Ayub; SATF 2005

Ramzan Mat Ayub; SATF 2005

The voltage required to achieve a threshold voltage must be large Ramzan Mat Ayub; SATF 2005 The voltage required to achieve a threshold voltage must be large enough to firstly achieve flatband condition, then accommodate the charge in the depletion region and finally to induce the inverted region

Ramzan Mat Ayub; SATF 2005 Example Calculate the threshold voltage for MOS strcuture described in example 1 and 2, including the effect of flatband voltage. If Al is used as gate material, Фms=-0.9V for NA=1015cm-3. Assume the interface charge of 5 x 1011 q (C/cm2). Q6, Tutorial 1