CPRE 583 Reconfigurable Computing Lecture 6: 9/9/2011 (VHDL Overview 3 ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

Announcements/Reminders MP1: will be released by right after class today VERY tentatively due next Friday 9/16. I’ll see how the class is progressing next Wed before giving a solid due date. HW1: will due midnight tonight (Fri 9/9) Mini literary survey assigned PowerPoint tree due: Fri 9/23 by class, so try to have to me by 9/22 night. My current plan is to summarize some of the classes findings during class. Final 5-10 page write up on your tree due: Fri 9/30 midnight.

Literary Survey Start with searching for papers from 2008-2011 on IEEE Xplorer: http://ieeexplore.ieee.org/ Advanced Search (Full Text & Meta data) Find popular cross references for each area For your topic try to identify 1-2 good survey papers For topic Identify 2-3 core Problems/issues For each problem identify 2-3 Approaches for addressing For each approach identify 1-2 papers that Implement the approach.

Literary Survey: Example Structure Hardware Accelerated Bioinformatics P1 P2 P3 A1 A2 A3 A1 A2 A1 A2 I1 I1 I2 I1 I1 I1 I1 I2 I1 5-10 page write up on your survey tree

Fall 2010 Student Example Network Intrusion Detection Systems detection accuracy signatures The Study on Network Intrusion Detection System of Snort heuristics An FPGA-Based Network Intrusion Detection Architecture adaptability to new threats neural networks Network Intrusion Detection Method Based on Radial Basic Function Neural Network principal component analysis An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System support vector machine Network Intrusion Detection Based on Support Vector Machine Network Intrusion Detection Method Based on Agent and SVM

Common Questions

Common Questions

Overview Introduction to State machines Jump start introduction to MP1

Finite State Machine (FSM) Design Model of computation High level application example (Networking) Two major types Moore Mealy Detailed view of application example

Finite State Machines What types of applications are they well suited Streaming pattern recognition Sequential event based control logic Allow hardware designer to reason about things in small pieces

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM src port IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM dest port src port IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM length dest port src port IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 1 length dest port src port IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 2 Data 1 length dest port src port IP dest IP src

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Data 3 Data 2 Data 1 length dest port src port IP dest

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert Data 3 Data 2 Data 1 length dest port src port IP dest

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert r o C length dest port src port IP dest

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert n r o C length dest port src port

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert Alert!! ! n r o C length dest port

Streaming Network application (MP1) Process UDP packet headers (event driven) Detect patterns in payload (e.g. “Corn”) Modify payload based on header information FSM Send Alert Modify Packet ! n r o C length dest port

Moore and Mealy FSMs Moore: Output is only a function of the current state Mealy: Output is a function of the current state and input (“Mealy is more”)

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1101” State Name Start (0) 1 (0) 11 (0) 110 (0) 1101 (1) FSM output

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1101” Where to go on a given input 1 Start (0) 1 (0) 11 (0) 110 (0) 1101 (1)

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1101” 1 Start (0) 1 (0) 11 (0) 110 (0) 1101 (1) State: Start S_1 Output: 0 0 Input: 1 ? NextState: S_1 ?

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “1101” 1 1 1 Start (0) 1 (0) 11 (0) 110 (0) 1101 (1) 1 1 State: Start S_1 S_11 S_110 S_1101 Output: 0 0 0 0 1 Input: 1 1 0 1 ? NextState: S_1 S_11 S_110 S_1101 ?

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “0101”

Moore FSM Moore: Output is only a function of the current state Example detect every occurrence of “0101” 10 (0) 1 010 (0) 1010 (1) 1 Start (0) (0) 1 1 1 1

Mealy FSM Moore: Output a function of the current state, and input Example detect every occurrence of “1011” State Name 1 11 011 1011

Mealy FSM Moore: Output a function of the current state, and input Example detect every occurrence of “1101” Input output 1/0 1 11 110 1101 0/0 Start

Mealy FSM Mealy: Output a function of the current state, and input Example detect every occurrence of “1101” 1/0 1/0 0/0 1 11 110 1101 0/0 0/0 1/0 Start 1/1 0/0

FSM: General Circuit Architecture Let: X be inputs Z be outputs State(t) be the state of the FSM at the current time State(t+1) be the next state of the FSM δ be the transition between states State(t+1) = δ(State(t), X) Output Moore: Z(State(t)) Mealy: Z(State(t), X) x=1/z=0 1/0 S1 S2 0/1 z=0 0/0

FSM: General Circuit Architecture Moore Combinational Logic Z(State(t)) Z(State(t),X) Inputs: X Outputs Mealy State Storage DFF Next State State(t+1) = δ(State(t), X) State(t) DFF

VHDL: IF and CASE constructs IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) sel = b“0” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; x”C” 4 2:1 Mux in_0 4 out_1 x”C” 4 x”D” in_1

VHDL: IF and CASE constructs Mapping a CASE statement to a 4:1 Mux CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => END CASE; sel = b“10” 2 x”C” 4 in_0 4:1 Mux 4 x”D” in_1 4 out_1 x”7” 4 x”7” in_2 4 x”2” in_3 Why do we need others here?

VHDL: IF and CASE constructs Mapping a CASE statement to a 1:4 Decoder CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => WHEN state_1011 => --similar code END CASE; on 2:1 Mux 1:4 Decoder out_0 off 2:1 Mux out_1 “10” 2 state on 2:1 Mux out_2 out_3 off 2:1 Mux Enumerated Type State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”}

VHDL: IF and CASE constructs Mapping a CASE statement to a 1:4 Decoder CASE state is WHEN state_1 => IF (sel = ‘0’) THEN mux_out <= ‘1’; ELSE mux_out <= ‘0’; END IF; WHEN state_11 => -- similar code WHEN state_011 => WHEN state_1011 => --similar code END CASE; on 2:1 Mux 1:4 Decoder out_0 off 2:1 Mux out_1 “00” 2 state off 2:1 Mux out_2 out_3 off 2:1 Mux Enumerated Type State = {state_1, state_11, state_011, state_1011} = {“00”, ”01”, ”10”, ”11”}

FSM: General Circuit Architecture Moore Combinational Logic Z(State(t)) Z(State(t),X) Inputs: X Outputs Mealy State Storage DFF Next State State(t+1) = δ(State(t), X) State(t) DFF

VHDL for Mealy (“1101”) Example -- Store the “state” Update_State: process(clk) begin if(clk’event and clk=‘1’) then state <= next_state; end if; end process Update_State; state next_state DFF

VHDL for Mealy (“1101”) Example -- Compute combinational logic Combinational: process(x, state) begin case state is when state_1 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1; else next_state <= state_11; end if; when state_11 => z <= ‘0’; next_state <= state_011 ; Compute output Compute next_state 1/0 1/0 0/0 1 11 011 1011 0/0 0/0 1/0 Start 1/1 0/0

VHDL for Mealy (“1101”) Example when state_011 => if(x = ‘0’) then z <= ‘0‘; next_state <= state_1011; else next_state <= state_011; end if; when state_1011 => z <= ‘0’; next_state <= state_1; z <= ‘1‘; next_state <= state_11; end case; end process Combinational; 1/0 1/0 0/0 1 11 011 1011 0/0 1/0 1/1 0/0

Network Processing Example: UDP UDP – User Datagram Protocol Popular protocol for sending data over the internet (TCP is popular another protocol) Typical encapsulated within IP (Internet Protocol) UDP/IP Gives no guarantee of delivery Relies on application layer to implement reliability Unlike TCP which has reliably delivery build in. Reference for more info on IP and UDP details http://www.freesoft.org/CIE/ RCFs Course

Destination IP Address UDP/IP Packet Format Ver IHL TOS Total Length Note: flags 3 bits Identification flags fragment offset IP Header UDP Protocol = 17 TTL Protocol Header Checksum Source IP Address Destination IP Address Options Padding Source Port Destination Port UDP Header UDP length (bytes) = UDP header+payload Length Checksum Byte1 Byte2 Byte3 Byte4 Payload 31 32-bits

Example: Network Processing Tasks Raise an alert signal when the pattern “corn!” is detected Return the number of times “corn!” is detected Place count value as the last byte of the payload

Streaming Network application (MP1) Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM Send Alert Modify Packet ! n r o C length dest port

Architecture Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload Draw out logic, and data flow!!! Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Architecture Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Alert FSM Design Alert signal when the pattern “corn!” is detected Z = {Alert} “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

Alert FSM Design Alert signal when the pattern “corn!” is detected Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

Alert FSM Design Alert signal when the pattern “corn!” is detected Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care UDP ports 1,“c”/0,0,0 1,“o”/0,0,0 1,“r”/0,0,0 1,“n”/0,0,0 1,”?”/0,0,0 1,”?”/0,0,0 c o r n ! IPH_5 UDP length 1,others/0,0,0 1,”?”/0,1,length IPH_2 1,others/0,0,0 1,others/0,0,0 1,”?”/0,0,0 1,others/0,0,0 Start IP 1,“!”/1,0,0 Start

Architecture Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

Next Class VHDL overview 4 Avoiding simulation differing from HW implementation

MP1 Jumpstart

Questions/Comments/Concerns