With Thermal Code inputs

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Presentation transcript:

With Thermal Code inputs Systolic Sorter With Thermal Code inputs

Overview What is the Min/Max cell What is the Sorter Why are you doing this What is left to do Demos

Min Max Cell Inputs are in thermometer code This makes comparison easy Let X1=0011 X2=0111 0011 0011 &0111 +0111 0011=min 0111=max Tradeoff is more bits/input

Sorter M inputs each N bits wide Inputs on right Outputs on top Little squares are registers (we’ll get there in a bit)

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Sorter Dataflow

Work With Muayad He has built same sorter with memristors I need to calculate Power Area Speed Compare to his results

Left for me Get code working Devise decent testbench

Future Cells have more functionality (different functions) External control of cells New connections Instructions travel with data

Demo Cell on FPGA Workflow on QuestaSim on (Redhad servers) Vivado schematic QuestaSim schematics