Design: architecture selection plus biasing/sizing Verification: use analysis and simulation to verify operating points, specifications, robustness Fabrication: Characterization: detailed verification by bench test Manufacturing: Final test: fast test of select specs

For each transistor: the designer can control W, L, and two of the 4 terminal voltages, the other two being reference and output. If there are N transistors, this leads to 4N degrees of freedom in design. But, in most designs, we tie the bulk to either source or a fixed voltage (VDD or VSS). For L, we mostly use L = 1.5Lmin or L = 2Lmin This leaves W/L and Veff as true choices. But, ID = K’ (W/L) Veff^2. If several transistors are stacked, they all have the save current. If ID is used as design parameter, d.o.f. is significantly reduced.

So, we use (W/L) and path currents as design parameters. Path current = current in a VDDVSS path N+M d.o.f. For NMOS and PMOS as counter-partner, we typically use very simple relationships in (W/L) determined by mn and mp ratio. This cuts N by roughly half. For differential circuit, it is required that the left side and the right side are matched. This cuts both N and M by a factor of 2.  Design for the quarter circuit.

Some calculations related to Common Source amplifier lab

Veff1 + |Veff2| = VDD – OSR For VDD = 5, OSR>=4, Vomin = Veff1 Vomax = VDD – |Veff2| Output swing range: VDD – Veff1 – |Veff2| Veff1 + |Veff2| = VDD – OSR For VDD = 5, OSR>=4,  Veff1 + |Veff2| <= 1 M2 vo 10m CL M1 Vin M1 is in signal path, needs small Veff and large gm M2 is current mirror transistors, needs large Veff for robustness. So target: Veff1 ~ 0.3, |Veff2| ~0.7Veff^2 ratio  5

Positive slew rate SR+ = I2Q/CLtot Negative slew rate SR- = (I1max-I2Q)/CLtot I1max can be very large when Vin is very large. So, SR- is unknown but is not the limit. From SR+, I2Q = SR+ * CLtot To accommodate parasitics: I2Q = SR+ * 1.2CLtot 40*1.2*5=240m Current mirror ratio: 1:24

GBW = gm1 / CLtot gm1 = GBW * CLtot = GBW * 1.2CL =40*2*10^6*1.2*5*10^-12  0.0015 gm1^2 = K’ (W/L) 4*I1Q = K’ (W/L) 4*I2Q W/L = 0.0015^2/(60e-6*4*240e-6)  39 For input transistor, use L = 1.5*Lmin = 0.9 W=39*0.9  35 Can use W/L = (6m/0.9m) x 6 or (9/0.9)x4 Check Veff: {240/(60)/(36/0.9)}^0.5=0.1^0.5, OK

For the counter partner PMOS M2: (W/L)p = (W/L)n * mp/mn * (Veffn/Veffp)^2 = 39 * 3 * (1/5)  40 * 3 /5 8*3 = 24 If we choose L=2Lmin = 1.2 W = 24*1.2 = 7.2 * 4  (W/L)M2 = 7.2/1.2 with multiplier 4 The diode connection can have 7.2/7.2

So Vin has to be very accurately selected to have the right Q-point. VDD VDD Since the amplifier is supposed to have high gain from Vin to Vo, a small error in Vin can cause large change in Vo, thus pushing Vo to be either very high (M2 in triode) or very low (M1 in triode). So Vin has to be very accurately selected to have the right Q-point. Two ways for this: M2 10 vo CL VoQ – + M1 VinQ

Use a high gain in VCVS, eg, 10^4. VDD VDD You can either do a fine step sweep near the computed VinQ = Veff+Vt, to find the right VinQ that make VoQ near middle of OSR; Or use the VCVS feedback on the previous page to automatically generate VinQ. Use a high gain in VCVS, eg, 10^4. After generation, replace by the connection on this page. M2 vo 10 CL M1 ~ VinQ With this, do DC, AC, and transient analysis.