UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017 Lecture 5: FPGA UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2017 Some slides for this lecture courtesy of Prof. Tinoosh Mohsenin, UMBC UCSD ECE 111, Prof. Koushanfar, Fall'17

Different Computing Systems UCSD ECE 111, Prof. Koushanfar, Fall'17

Memory Arrays Efficiently store large amounts of data 3 common types: Dynamic random access memory (DRAM) Static random access memory (SRAM) Read only memory (ROM) M-bit data value read/ written at each unique N-bit address The previous sections introduced arithmetic and sequential circuits for manipulating data. Digital systems also require memories to store the data used and generated by such circuits. Registers built from flip-flops are a kind of memory that stores small amounts of data. This section describes memory arrays that can efficiently store large amounts of data. The green slides are based on the Digital Design book by Harris&Harris Slides downloaded from: http://hron.fei.tuke.sk/~adam/cas/

Memory Arrays 2-dimensional array of bit cells Each bit cell stores one bit N address bits and M data bits: 2N rows and M columns Depth: number of rows (number of words) Width: number of columns (size of word) Array size: depth × width = 2N × M

Memory Array Example 22 × 3-bit array Number of words: 4 Word size: 3-bits For example, the 3-bit word stored at address 10 is 100

Memory Arrays

Memory Array Bit Cells Z Memory arrays are built as an array of bit cells, each of which stores 1 bit of data. Each bit cell is connected to a wordline and a bitline. For each combination of address bits, the memory asserts a single wordline that activates the bit cells in that row. When the wordline is HIGH, the stored bit transfers to or from the bitline. Otherwise, the bitline is disconnected from the bit cell. The circuitry to store the bit varies with memory type. To read a bit cell, the bitline is initially left floating (Z). Then the wordline is turned ON, allowing the stored value to drive the bitline to 0 or 1. To write a bit cell, the bitline is strongly driven to the desired value. Then the wordline is turned ON, connecting the bitline to the stored bit. The strongly driven bitline overpowers the contents of the bit cell, writing the desired value into the stored bit.

Memory Array Bit Cells Z 1 Z

Memory Array Wordline: like an enable single row in memory array read/written corresponds to unique address only one wordline HIGH at once Figure shows the internal organization of a 4 × 3 memory array. Of course, practical memories are much larger, but the behavior of larger arrays can be extrapolated from the smaller array. During a memory read, a wordline is asserted, and the corresponding row of bit cells drives the bitlines HIGH or LOW. During a memory write, the bitlines are driven HIGH or LOW first and then a wordline is asserted, allowing the bitline values to be stored in that row of bit cells. For example, to read Address 10, the bitlines are left floating, the decoder asserts wordline2, and the data stored in that row of bit cells (100) reads out onto the Data bitlines. To write the value 001 to Address 11, the bitlines are driven to the value 001, then wordline3 is asserted and the new value (001) is stored in the bit cells.

Types of Memory Random access memory (RAM): volatile Read only memory (ROM): nonvolatile Memories are classified based on how they store bits in the bit cell. The broadest classification is random access memory (RAM) versus read only memory (ROM). RAM is volatile, meaning that it loses its data when the power is turned off. ROM is nonvolatile, meaning that it retains its data indefinitely, even without a power source.

RAM: Random Access Memory Volatile: loses its data when power off Read and written quickly Main memory in your computer is RAM (DRAM) Historically called random access memory because any data word accessed as easily as any other (in contrast to sequential access memories such as a tape recorder) RAM is called random access memory because any data word is accessed with the same delay as any other. In contrast, a sequential access memory, such as a tape recorder, accesses nearby data more quickly than faraway data.

ROM: Read Only Memory Nonvolatile: retains data when power off Read quickly, but writing is impossible or slow Flash memory in cameras, thumb drives, and digital cameras are all ROMs Historically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Flash memory and other types of ROMs. ROM is called read only memory because, historically, it could only be read but not written. These names are confusing, because ROMs are randomly accessed too.

Types of RAM DRAM (Dynamic random access memory) SRAM (Static random access memory) Differ in how they store data: DRAM uses a capacitor SRAM uses cross-coupled inverters

DRAM Data bits stored on capacitor Dynamic because the value needs to be refreshed (rewritten) periodically and after read: Charge leakage from the capacitor degrades the value Reading destroys the stored value Upon a read, data values are transferred from the capacitor to the bitline. Upon a write, data values are transferred from the bitline to the capacitor. Reading destroys the bit value stored on the capacitor, so the data word must be restored (rewritten) after each read.

DRAM As shown in Figure (a), when the capacitor is charged to VDD, the stored bit is 1; when it is discharged to GND (Figure b), the stored bit is 0. The capacitor node is dynamic because it is not actively driven HIGH or LOW by a transistor tied to VDD or GND.

SRAM Static RAM (SRAM, pronounced “es-ram”) is static because stored bits do not need to be refreshed. Figure shows an SRAM bit cell. The data bit is stored on cross-coupled inverters. When the wordline is asserted, both nMOS transistors turn on, and data values are transferred to or from the bitlines.

Memory Arrays Review DRAM bit cell: SRAM bit cell:

ROM: Dot Notation Read only memory (ROM) stores a bit as the presence or absence of a transistor. To read the cell, the bitline is weakly pulled HIGH. Then the wordline is turned ON. If the transistor is present, it pulls the bitline LOW. If it is absent, the bitline remains HIGH. Note that the ROM bit cell is a combinational circuit and has no state to “forget” if power is turned off. The contents of a ROM can be indicated using dot notation. A dot at the intersection of a row (wordline) and a column (bitline) indicates that the data bit is 1. For example, the top wordline has a single dot on Data1, so the data word stored at Address 11 is 010.

ROM Storage Conceptually, ROMs can be built using two-level logic with a group of AND gates followed by a group of OR gates.

ROM Logic Data2 = A1 Å A0 Data1 = A1 + A0 Data0 = A1A0

Example: Logic with ROMs Implement the following logic functions using a 22 × 3-bit ROM: X = AB Y = A + B Z = A B

Example: Logic with ROMs Implement the following logic functions using a 22 × 3-bit ROM: X = AB Y = A + B Z = A B

Logic with Any Memory Array Data2 = A1 Å A0 Data1 = A1 + A0 Data0 = A1A0

Logic with Memory Arrays Implement the following logic functions using a 22 × 3-bit memory array: X = AB Y = A + B Z = A B

Logic with Memory Arrays Implement the following logic functions using a 22 × 3-bit memory array: X = AB Y = A + B Z = A B

Logic with Memory Arrays Called lookup tables (LUTs): look up output at each input combination (address) Although they are used primarily for data storage, memory arrays can also perform combinational logic functions. Memory arrays used to perform logic are called lookup tables (LUTs). Figure shows a 4-word × 1-bit memory array used as a lookup table to perform the function Y= AB. Each address corresponds to a row in the truth table, and each data bit corresponds to an output value.

Logic Arrays PLAs (Programmable logic arrays) AND array followed by OR array Combinational logic only Fixed internal connections FPGAs (Field programmable gate arrays) Array of Logic Elements (LEs) Combinational and sequential logic Programmable internal connections Programmable logic arrays (PLAs) implement two-level combinational logic in sum-of-products (SOP) form. PLAs are built from an AND array followed by an OR array. For example, ROMs can be viewed as a special case of PLAs. A field programmable gate array (FPGA) is an array of reconfigurable gates. Using software programming tools, a user can implement designs on the FPGA using either an HDL or a schematic. FPGAs are more powerful and more flexible than PLAs for several reasons. They can implement both combinational and sequential logic.

PLAs X = ABC + ABC Y = AB

PLAs: Dot Notation

FPGA: Field Programmable Gate Array Composed of: LEs (Logic elements): perform logic IOEs (Input/output elements): interface with outside world Programmable interconnection: connect LEs and IOEs Some FPGAs include other building blocks such as multipliers and RAMs FPGAs are built as an array of configurable logic elements (LEs), also referred to as configurable logic blocks (CLBs). Each LE can be configured to perform combinational or sequential functions. The LEs are surrounded by input/output elements (IOEs) for interfacing with the outside world. LEs can connect to other LEs and IOEs through programmable routing channels.

General FPGA Layout This figure shows a general block diagram of an FPGA.

LE: Logic Element Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential logic Multiplexers: connect LUTs and flip-flops

Altera Cyclone IV LE The Spartan CLB has: 1 four-input LUT 1 registered output 1 combinational output

FPGA Design Flow Using a CAD tool (such as Altera’s Quartus II) Enter the design using schematic entry or an HDL Simulate the design Synthesize design and map it onto FPGA Download the configuration onto the FPGA Test the design

UCSD ECE 111, Prof. Koushanfar, Fall'17 FPGAs Large array of Configurable Logic Blocks (CLB) connected via programmable interconnects FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Logic Design Using Multiplexers Using the mux as a lookup table UCSD ECE 111, Prof. Koushanfar, Fall'17

Logic using multiplexers Reducing the size of the mux UCSD ECE 111, Prof. Koushanfar, Fall'17

Virtex-5 Configuration Logic Block (CLB) Used to realize logic functions Each CLB is connected to a switch matrix Each CLB contains a pair of slices. Every slice contains: 4 Look Up Tables (LUTs) 4 registers Wide-function multiplexer Carry Logic UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Look Up Tables (LUTs) A computation can be represented as a Boolean equation A Boolean equation can be represented as a truth table Truth tables are the computational heart of the FPGAs A LUT is a hardware element that can easily implement a truth table UCSD ECE 111, Prof. Koushanfar, Fall'17

Basic Programmable Devices UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Generic Xilinx FPGA Architecture UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Spartan-3 FPGA Family Name UCSD ECE 111, Prof. Koushanfar, Fall'17 Pictures courtesy of Xilinx

Summary of Spartan-3 FPGA Family Attributes UCSD ECE 111, Prof. Koushanfar, Fall'17 Table courtesy of Xilinx

Overview of the Digilent S3 Board The Digilent S3 board is based on a Spartan-3 device (usually an XC3S200) and has an array of built-in peripherals. Xilinx Spartan-3 XC3S200 FPGA device (XC3S200FT256) 2M-bit Xilinx XCF02S platform flash configuration PROM Two 256K-by-16 asynchronous SRAM devices VGA display port RS-232 serial port RS-232 transceiverlvoltage-level convertor Second RS-232 transmit and receive channel PSI2mouse/keyboardport Four-digit seven-segment LED display UCSD ECE 111, Prof. Koushanfar, Fall'17

Overview of Development Flow Chart courtesy of the Course Textbook UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 FPGA vs. ASIC UCSD ECE 111, Prof. Koushanfar, Fall'17

Standard cell based IC Vs. Custom Design IC Design using standard cells Standard cells come from library provider Many different choices for cell size, delay, and leakage power Many EDA tools to automated this flow Shorter design time Custom design IC: Design all by yourself Higher performance UCSD ECE 111, Prof. Koushanfar, Fall'17

Standard Cell based VLSI Design Flow Front End System specification and architecture HDL coding & behavioral simulation Synthesis & gate level simulation Back End Placement & routing Design Rule Check (DRC), Layout vs Schematic (LVS) Dynamic simulation & static analysis UCSD ECE 111, Prof. Koushanfar, Fall'17

Simple Diagram of the Front-end Design Flow UCSD ECE 111, Prof. Koushanfar, Fall'17

Simple Diagram of the Back-end Design Flow UCSD ECE 111, Prof. Koushanfar, Fall'17

Flow of Placement & Routing UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Import Needed Files Gate level Verilog (.v) Geometry information (.lef) Timing information (.lib) UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Floorplan Size of chip Location of pins Location of main blocks Power supply: give enough power for each gate UCSD ECE 111, Prof. Koushanfar, Fall'17

Floorplan of a Single Processor UCSD ECE 111, Prof. Koushanfar, Fall'17

Placement & In-placement Optimization UCSD ECE 111, Prof. Koushanfar, Fall'17

Placement of a Single Processor UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Clock Tree UCSD ECE 111, Prof. Koushanfar, Fall'17

Clock Tree of Single Processor UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Routing UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Routing UCSD ECE 111, Prof. Koushanfar, Fall'17

Layout of a Single Processor UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Clock Tree in FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 FPGA vs. ASIC Summary UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 FPGA vs. DSP UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 FPGA vs. DSP UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Current Trend UCSD ECE 111, Prof. Koushanfar, Fall'17

Target Many-core Architecture UCSD ECE 111, Prof. Koushanfar, Fall'17

167-processor Multi-voltage Computational Chip UCSD ECE 111, Prof. Koushanfar, Fall'17

Summary of the 167 Many-core Chip UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Design Flow UCSD ECE 111, Prof. Koushanfar, Fall'17

UCSD ECE 111, Prof. Koushanfar, Fall'17 Design Flow UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17

Features & Specifications of FPGAs UCSD ECE 111, Prof. Koushanfar, Fall'17