GTK TDC design and characterization notes Gianluca Aglieri Rinella

Updates on 6 4 2011, Since 30 03 2011

Modifications to coarse time unit Several synchronization issues got evident when analyzing fastest running condition parallel_load signal must be used First stage of registers latches fine codes, pixel addresses and pileup with parallel_load signal Second stage of registers latches fine codes, pixel addresses and pileup on synchronized trailing pulse In the fastest case the level-pulse circuit might fail because asynchronous input pulses can be so close that no edges are seen Reset of synchronizer circuits added Lead edge synchronized path can be reset with parallel_load Trail edge path cannot use parallel_load but it can self reset because the duration of the input trail edge pulse is constrained Level-pulse circuit on the trail edge pulse not needed anymore

Modifications to coarse time unit ToT counter logic needs revision because in the fastest cases the LeadPulseSyncR and TrailPulseSyncR might be asserted at the same clock transition ToT code of 0 shall be latched in this case

Considerations on parallel_load Parallel_load is launched by the hit arbiter control at the rising edge of the clock Data path: FF and driving gate Inverter at the input of coarse time unit DSRFF in hit arbiter is DFF_E 186 ps + 1.33*(2 fF) ~= 190 ps Driving gate: OR2_D Cload ~= 1000 um * 0.2139 fF/um ~= 214 fF 119 + 2.62 * Cload ~= 680 ps Notice: this should be made stronger (OR2_E has same footprint and would give 458 ps worst case tpd) Receiving gate INVERT_I and AND logic Cload <= 50 fF Tpd <= 2*100 ps = 200 ps Total worst case delay (slow process, 125 C, 1.4V) ~= 1080 ps

Updated block diagram 1x coarseTimeUnit LeadFineCode LeadCoarseCode Count<10:0> Count<0> 5 11 SynchRising LevelPulseRising 1 parallel_load parallel_load LeadPulseSyncR EN D<4:0> D Q D Q EN D<10:0> D Q LeadFineCode LeadEdge LeadCoarseCode Clk Q<4:0> Clk Q<10:0> TrailPulseSyncR EN D<4:0> Clk Clk Clk LeadFineCode 11 Clk Q<4:0> SynchFalling LevelPulseFalling LeadPulseSyncF D parallel_load D Q D Q EN 5 D Q D<4:0> parallel_load EN TrailFineCode Clk Q 1 Clk Q<4:0> TrailPulseSyncR Clk Clk Clk TotCounter EN D<4:0> LeadPulseSyncR Reset TrailFineCode Clk SynchRising Clk Count<3:0> Q<4:0> TrailPulseSyncR D Q D Q TrailPulseSyncR parallel_load EN D<3:0> 5 TrailEdge EN D<4:0> TotCoarseCode PixelAddress Clk Q<3:0> Clk Q<4:0> Clk Clk Count<0> 1 TrailPulseSyncR 4 EN D<4:0> SynchFalling PixelAddress Clk TrailPulseSyncF D Q<4:0> D Q D Q EN parallel_load 5 Clk Q EN D<4:0> 1 PileUp Clk Clk Clk Q<4:0> TrailPulseSyncR EN D<4:0> parallel_load_i PileUp TrailPulseSyncR Clk FifoWrite parallel_load FifoWrite Q<4:0> PixelFifoReady Clk MissedHitsCount MissedHitsCount

Status and activities Revision of HDL with the described changes almost finished Includes serial readout of data storage registers TO DO Revision of ToT counter unit The specific situation of simultaneous assertion of LeadPulseSyncR and TrailPulseSyncR was not correctly handled in previous design Block generating write to FIFO command and counting the hits lost because of FIFO full Verification test bench Directed testing of all hierarchy elements and for the global coarse time unit Testing with random stimulus from hit generator

Last updated 30 03 2011

Propagation delays of buffers 32b fine hit register Clock inputs are buffered with two custom inverters DLLpdINV1, DLLpdINV3 Delays characterized with parasitics extracted from the 32b layout Rise time of buffer output extracted for hit register cell simulation TT, 27 C, 1.2V NOPARAS SS, 100 C, 1.1V PARAS TT, 27 C, 1.2 V FF, -30 C, 1.65 V DLLpdINV1 tpdr [ps] 58 81 64 38 tpdf 57 90 63 33 DLLpdINV3 42 134 97 41 154 103 60 tr 248 180 105 gianluca.aglieri.rinella@cern.ch

Propagation delays of D FF Dff_se_layout2b_hitreg Fine code register built with custom DFF cell Dff_se_layout2b_hitreg Delays from clk to Q output characterized with 50 fF load, abs max input capacitance of the Encoder block. No parasitics Q_ used only in serial readout. Loaded with a distributed RC model of the long lines to the coarse units serial input, next slide (**) Typ input rise time from the simulation of the input buffer 225 ps Cl=50 fF SS, 100 C, 1.1V PARAS TT, 27 C, 1.2 V FF, -30 C, 1.65 V Q tpdr [ps] 574 349 166 tpdf 422 283 141 Cl = (**) SS, 100 C, 1.1V PARAS TT, 27 C, 1.2 V FF, -30 C, 1.65 V _Q tpdr [ps] 2206 1567 831 tpdf 1937 1065 540 gianluca.aglieri.rinella@cern.ch

Estimates of load on Q_ MQ wires ~1000 um length, 0.4 um width, 2500 squares Max cap load 0.2139 fF/um, 214 fF total Rs = 0.0373 +- 0.0082 Ohm (temp coeff. 0.3 %/K) Rtyp = 93 +- 20.5 Ohms Pi model of a quarter length wire C = 1/8 * 214 fF = 26.75 fF R ~= 25 Ohm Load gate input capacitance 1 < Cg < 7 fF (negligible) gianluca.aglieri.rinella@cern.ch

Functional models with delays Functional models with delays written for cells Gian_DLLpdINV1 Gian_DLLpdINV3 Dff_se_layout2b_hitreg Delays included in specify blocks of the verilog functional views Delays from analog simulation described in previous slides gianluca.aglieri.rinella@cern.ch