6-bit 500 MHz flash A/D converter with new design techniques

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Presentation transcript:

6-bit 500 MHz flash A/D converter with new design techniques C.W. Hsu and T.H. Kuo, ” 6-bit 500MHz flash A/D converter with new design techniques,” IEEE Proceedings Devices and Systems Circuits , Page(s) 460-464, Oct. 2003. Postgraduate : Ting-Yao Hsu

Outline Proposed ADC Architecture New autozeroing with interpolation technique Negative impedance compensation technique Measurement results Conclusion

Proposed ADC Architecture Fig.1. Architecture of proposed ADC

New autozeroing with interpolation technique Fig.2. Simple autozeroing comparator

New autozeroing with interpolation technique Fig.3. Input stage of the conventional autozeroing technique

New autozeroing with interpolation technique Fig.4. Input stage of NAI

Negative impedance compensation technique Fig.5. Interpolation circuit diagram with NIC

Negative impedance compensation technique Fig.6. Model diagram of NIC analysis

Negative impedance compensation technique Fig.7. NIC circuit diagram

Fig.8. DNL and INL for the ADC at 500 Msample/s Measurement results Fig.8. DNL and INL for the ADC at 500 Msample/s

Measurement results

Conclusion NAI solves the problems of the autozeroing with interpolation technique. NIC can improve the ADC speed and maintain the desired interpolation effect.