Irakli MANDJAVIDZE DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette, France SRP: Architecture Irakli MANDJAVIDZE DAPNIA, CEA Saclay, 91191 Gif-sur-Yvette, France Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05

Overview SRP in ECAL Off-Detector Electronics The Selective Read-out Processor The SRP architecture The Algorithm Board Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05

SRP in ECAL OFF-Detector Electronics Partial trigger primitives Trigger Towers Front-ends 108 TCC L1 accept L1 Trigger All event data Classification flags: 3bit/TT 54 CCS TCS SRP 12 algorithm boards Input pipeline delay of 6.4µs/RU TTC 54 DCC sTTS Read-out flags: 3bit/TT Operation Receive TT flags from TCCs Exchange frontier TT flags among ABs Execute SR algorithm Deliver SR flags to DCCs Selected event data HLT & DAQ Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05

The Selective Read-out Processor Architecture A 6U VME64x crate 12 identical Algorithm Boards 1-slot VME64x compliant four ECAL partitions Crate controller Boundary scan controller (?) Operation Receive TT flags from 108 TCCs from up to 12 TTCs per AB Exchange frontier TT flags among ABs among up to 8 ABs Execute SR algorithm Deliver SR flags to 54 DCCs to up to 6 DCCs per AB Interfaces Optical serial links for: TCC-AB and AB-DCC AB-AB A TTC interface per AB A TTS interface per partition sTTS signals of 3 ABs merged ... and sent by any of the ABs Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05

Parallel optic modules SRP Architecture Algorithm Board under development 2 boards expected in September SRP crate Left end-cap Left ½ barrel Right ½ barrel Right end-cap Rx: TCC input C B S A B A B A B A B A B A B A B A B A B A B A B A B Tx: DCC output Parallel optic modules Rx: AB input Four Partitions Tx: AB output TTC input TTS input1 RJ45 TTS input2 TTS output Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05

SNAP12 MSA pluggable parallel optic modules Algorithm Board P1 J0 P2 VME buffers Power supply Xilinx V2Pro xc2vp70-6-ff1704 BS controller & JTAG chain Core FPGA VME Serial links Algorithms FPROMs Memory Clock synthesizer TCS interface SNAP12 MSA pluggable parallel optic modules QPLL TTCrx T T C Rx D C C Tx A B Rx A B Tx RJ45 connectors Aux. connector TrueLite TTS IN TTS IN TTS OUT Cons., JTAG Ethernet O/E Same hardware for AB and AB Tester Irakli.MANDJAVIDZE@cea.fr ODE Workshop, LIP, 07-08/04/05