Assembly Language for x86 Processors Section 3 (c) Pearson Education, 2010. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.

What's Next Internal microprocessor architecture Registers Assembly Language introduction Assembly instructions Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

INTERNAL MICROPROCESSOR ARCHITECTURE Before a program is written or instruction investigated, internal configuration of the microprocessor must be known. In a multiple core microprocessor each core contains the same programming model. Each core runs a separate task or thread simultaneously.

A thread consists of a program counter, a register set, and a stack space. A task shares with peer threads its code section, data section, and operating system resources of your written code will be described in the execution cycle

What stack space is!! When a program starts executing, a certain contiguous section of memory is set aside for the program called the stack. Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Program Template OS resources Data section Code section TITLE Program Template (Template.asm) ; Program Description: ; Author: ; Creation Date: ; Revisions: ; Date: Modified by: INCLUDE Irvine32.inc .data ; (insert variables here) .code main PROC ; (insert executable instructions here) exit main ENDP ; (insert additional procedures here) END main OS resources Data section Code section Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

The Programming Model 8086 through Core2 considered program visible. registers are used during programming and are specified by the instructions Other registers considered to be program invisible. not addressable directly during applications programming 80286 and above contain program-invisible registers to control and operate protected memory. and other features of the microprocessor

What's Next Internal processor architecture Registers Assembly Language introduction Assembly instructions Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Basic Microcomputer Design Why we need registers!!!  clock synchronizes CPU operations control unit (CU) coordinates sequence of execution steps ALU performs arithmetic and bitwise processing Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

General-Purpose Registers Named storage locations inside the CPU, optimized for speed. Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Accessing Parts of Registers Use 8-bit name, 16-bit name, or 32-bit name Applies to EAX, EBX, ECX, and EDX Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Index and Base Registers Some registers have only a 16-bit name for their lower half: Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

programming model 8086 through Core2 microprocessor (1/5) Multipurpose Registers including the 64-bit extensions RAX - a 64-bit register (EAX), a 32-bit register (accumulator) ,(AX) 16-bit register (AX), or as either of two 8-bit registers (AH and AL). The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions.

programming model 8086 through Core2 microprocessor (2/5) RBX, addressable as RBX, EBX, BX, BH, BL. BX register (base index) sometimes holds offset address of a location in the memory system in all versions of the microprocessor RCX, as RCX, ECX, CX, CH, or CL. a (count) general-purpose register that also holds the count for various instructions is used in looping RDX, as RDX, EDX, DX, DH, or DL. a (data) general-purpose register holds a part of the result from a multiplication or part of dividend before a division

programming model 8086 through Core2 microprocessor (3/5) Register Organization of 8086 Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

programming model 8086 through Core2 microprocessor (4/5) RBP, as RBP, EBP, or BP. points to a memory (base pointer) location for memory data transfers RDI addressable as RDI, EDI, or DI. often addresses (destination index) string destination data for the string instructions RSI used as RSI, ESI, or SI. the (source index) register addresses source string data for the string instructions like RDI, RSI also functions as a general- purpose register

programming model 8086 through Core2 microprocessor (5/5) segment registers & special purpose registers Segment registers to address memory space  CS - points at the segment containing the current program code.  DS - generally points at segment where variables are defined.  ES - extra segment register, it's up to a coder to define its usage (used by some string instructions to hold destination data).  SS - points at the segment containing the stack of memory specified for the program/thread.  GS and FS - general purpose segments (for access by the program) special purpose registers  flags register - determines the current state of the microprocessor. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Status Flags (later) Carry Overflow Sign Zero Auxiliary Carry Parity unsigned arithmetic out of range Overflow signed arithmetic out of range Sign result is negative Zero result is zero Auxiliary Carry carry from bit 3 to bit 4 Parity sum of 1 bits is an even number Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Floating-Point, MMX, XMM Registers (later) Eight 80-bit floating-point data registers ST(0), ST(1), . . . , ST(7) arranged in a stack used for all floating-point arithmetic Eight 64-bit MMX registers Eight 128-bit XMM registers for single-instruction multiple-data (SIMD) operations Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Summary of registers General-Purpose Segment EIP – instruction pointer EAX – accumulator ECX – loop counter ESP – stack pointer ESI, EDI – index registers EBP – extended frame pointer (stack) Segment CS – code segment DS – data segment SS – stack segment ES, FS, GS - additional segments EIP – instruction pointer EFLAGS status and control flags each flag is a single binary bit

What's Next Internal processor architecture Registers Assembly Language introduction Assembly instructions Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Basic Elements of Assembly Language Integer constants Integer expressions Character and string constants Reserved words and identifiers (later) Directives and instructions (later) Instruction format Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Integer Constants Optional leading + or – sign binary, decimal, hexadecimal, or octal digits Common radix characters: h – hexadecimal d – decimal b – binary r – encoded real Examples: 30d, 6Ah, 42, 1101b Hexadecimal beginning with letter: 0A5h Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Integer Expressions Operators and precedence levels: Examples: Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Character and String Constants Enclose character in single or double quotes 'A', "x" ASCII character = 1 byte Enclose strings in single or double quotes "ABC" 'xyz' Each character occupies a single byte Embedded quotes: 'Say "Goodnight," Gracie' Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Instructions Assembled into machine code by assembler Executed at runtime by the CPU We use the Intel IA-32 instruction set An instruction contains: Label (optional) Mnemonic (required) Operand (depends on the instruction) Comment (optional) Def: Statement excuted by processor at runtime after the program has been loaded into memory and started. In process of scanning source program the assymbler assigns a numeric address to each program statement Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Labels Act as place markers Follow identifer rules marks the address (offset) of code and data Follow identifer rules Data label (when used in data area of program) must be unique within the source code file example: myArray (not followed by colon) Code label target of jump and loop instructions example: L1: (followed by colon) Labels are often used as a target for jumping and looping Ex: Target: mov ax, bx Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Mnemonics and Operands Instruction Mnemonics memory aid examples: MOV, ADD, SUB, MUL, INC, DEC Operands constant constant expression register memory (data label) Immediate values p.9 Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

Comments Comments are good! Single-line comments Multi-line comments explain the program's purpose when it was written, and by whom revision information tricky coding techniques application-specific explanations Single-line comments begin with semicolon (;) Multi-line comments begin with COMMENT directive and a programmer-chosen character end with the same programmer-chosen character Irvine, Kip R. Assembly Language for Intel-Based Computers, 2007.

What's Next Internal processor architecture Registers Assembly Language introduction Assembly instructions Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.

Instruction Set 80186 instruction set consists of the following instructions: Data moving instructions. Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. Logic - AND, OR, exclusive OR, shift/rotate and test. String manipulation - load, store, move, compare and scan for byte/word. Control transfer - conditional, unconditional, call subroutine and return from subroutine. Input/Output instructions. Other - setting/clearing flag bits, stack operations, software interrupts, etc Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

MOV Instruction Move from source to destination. Syntax: MOV destination, source Both operands must be the same size No more than one memory operand permitted CS, EIP, and IP cannot be the destination No immediate to segment moves No immediate as a destination mov al,wVal ; error mov ax,count ; error mov eax,count ; error Size al= 8bit wval= 16bit Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

MOV Instruction Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

MOV Instruction Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Your turn . . . Explain why each of the following MOV statements are invalid: ..code mov ds,45 mov eip,dVal mov 25,bVal mov bVal2,bVal immediate move to DS not permitted nut you could create label in thid memory segment EIP cannot be the destination immediate value cannot be destination memory-to-memory move not permitted Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Zero Extension The destination must be a register. When you copy a smaller value into a larger destination, the MOVZX instruction fills (extends) the upper half of the destination with zeros. mov bl,10001111b movzx ax,bl ; zero-extension Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Zero Extension Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

The destination must be a register. Sign Extension The MOVSX instruction fills the upper half of the destination with a copy of the source operand's sign bit. mov bl,10001111b movsx ax,bl ; sign extension Section1 > p 104 The destination must be a register. Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

XCHG Instruction XCHG exchanges the values of two operands. At least one operand must be a register. No immediate operands are permitted. Two operands must have the same size .data var1 WORD 1000h var2 WORD 2000h .code xchg ax,bx ; exchange 16-bit regs xchg ah,al ; exchange 8-bit regs xchg var1,bx ; exchange mem, reg xchg eax,ebx ; exchange 32-bit regs xchg var1,var2 ; error: two memory operands Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Arithmetic operations Addition and Subtraction INC and DEC Instructions ADD and SUB Instructions P 1:21 P 21:57 Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

INC and DEC Instructions Add 1, subtract 1 from destination operand operand may be register or memory INC destination Logic: destination  destination + 1 DEC destination Logic: destination  destination – 1 Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

INC and DEC Examples .data myWord WORD 1000h myDword DWORD 10000000h .code inc myWord ; 1001h dec myWord ; 1000h inc myDword ; 10000001h mov ax,00FFh inc ax ; AX = 0100h inc al ; AX = 0000h Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

ADD and SUB Instructions ADD destination, source Logic: destination  destination + source SUB destination, source Logic: destination  destination – source Same operand rules as for the MOV instruction Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

ADD and SUB Examples .data var1 DWORD 10000h var2 DWORD 20000h .code ; ---EAX--- mov eax,var1 ; 00010000h add eax,var2 ; 00030000h add ax,0FFFFh ; 0003FFFFh add eax,1 ; 00040000h sub ax,1 ; 0004FFFFh Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

Lets look at this example Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003.

42 69 6E 61 72 79 What does this say? Irvine, Kip R. Assembly Language for x86 Processors 6/e, 2010.